From 4a79e70470987ba54a16ab97eb25d664509550fc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 10 Jun 2018 14:08:00 +0200
Subject: Fix ice40 pip/switch locked performance issue

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 ice40/chip.cc   |  2 +-
 ice40/chip.h    | 21 +++++++--------------
 ice40/chipdb.py |  2 +-
 3 files changed, 9 insertions(+), 16 deletions(-)

(limited to 'ice40')

diff --git a/ice40/chip.cc b/ice40/chip.cc
index 0caabe0c..3a79d65f 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -97,7 +97,7 @@ Chip::Chip(ChipArgs args) : args(args)
     bel_to_cell.resize(chip_info.num_bels);
     wire_to_net.resize(chip_info.num_wires);
     pip_to_net.resize(chip_info.num_pips);
-    pips_locked.resize(chip_info.num_pips);
+    switches_locked.resize(chip_info.num_switches);
 }
 
 // -----------------------------------------------------------------------
diff --git a/ice40/chip.h b/ice40/chip.h
index 84b2196a..7e20a252 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -162,6 +162,7 @@ struct ChipInfoPOD
 {
     int width, height;
     int num_bels, num_wires, num_pips;
+    int num_switches;
     BelInfoPOD *bel_data;
     WireInfoPOD *wire_data;
     PipInfoPOD *pip_data;
@@ -411,7 +412,7 @@ struct Chip
     vector<IdString> bel_to_cell;
     vector<IdString> wire_to_net;
     vector<IdString> pip_to_net;
-    vector<bool> pips_locked;
+    vector<bool> switches_locked;
     Chip(ChipArgs args);
 
     ChipArgs args;
@@ -567,32 +568,24 @@ struct Chip
     {
         assert(pip != PipId());
         assert(pip_to_net[pip.index] == IdString());
+        assert(!switches_locked[chip_info.pip_data[pip.index].switch_index]);
         pip_to_net[pip.index] = net;
-        // Optimise?
-        for (int i = 0; i < chip_info.num_pips; i++) {
-            if (chip_info.pip_data[i].switch_index ==
-                chip_info.pip_data[pip.index].switch_index)
-                pips_locked[i] = true;
-        }
+        switches_locked[chip_info.pip_data[pip.index].switch_index] = true;
     }
 
     void unbindPip(PipId pip)
     {
         assert(pip != PipId());
         assert(pip_to_net[pip.index] != IdString());
+        assert(switches_locked[chip_info.pip_data[pip.index].switch_index]);
         pip_to_net[pip.index] = IdString();
-        // Optimise?
-        for (int i = 0; i < chip_info.num_pips; i++) {
-            if (chip_info.pip_data[i].switch_index ==
-                chip_info.pip_data[pip.index].switch_index)
-                pips_locked[i] = false;
-        }
+        switches_locked[chip_info.pip_data[pip.index].switch_index] = false;
     }
 
     bool checkPipAvail(PipId pip) const
     {
         assert(pip != PipId());
-        return !pips_locked[pip.index];
+        return !switches_locked[chip_info.pip_data[pip.index].switch_index];
     }
 
     IdString getPipNet(PipId pip) const
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index a92704eb..f6f73d99 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -451,7 +451,7 @@ print(",\n".join(tilegrid))
 print("};")
 
 print("ChipInfoPOD chip_info_%s = {" % dev_name)
-print("  %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo)))
+print("  %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo)))
 print("  bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
 print("  tile_grid_%s, &bits_info_%s" % (dev_name, dev_name))
 print("};")
-- 
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