From bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sun, 29 Mar 2020 10:27:42 +0200
Subject: ice40: Fix output register timing analysis for registered output
 enable

Wrong bits were being tested. [5:4] is what's controlling the output
enable path.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 ice40/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'ice40')

diff --git a/ice40/arch.cc b/ice40/arch.cc
index a43c4c21..6d07a949 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -1037,7 +1037,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             }
         }
         if (port == id_OUTPUT_ENABLE) {
-            if ((cell->ioInfo.pintype & 0x18) == 0x18) {
+            if ((cell->ioInfo.pintype & 0x30) == 0x30) {
                 return TMG_REGISTER_INPUT;
             } else {
                 return TMG_ENDPOINT;
-- 
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