From 6707b985b4b62cf201778735bb1fef3e12567ec9 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 12 Jun 2018 15:13:33 +0200
Subject: ice40: Add support for LC placement constraints in packer

Signed-off-by: David Shah <davey1576@gmail.com>
---
 ice40/pack_tests/place_constr.v | 54 +++++++++++++++++++++++++++++++++++++++++
 ice40/pack_tests/test.sh        |  3 ++-
 2 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 ice40/pack_tests/place_constr.v

(limited to 'ice40/pack_tests')

diff --git a/ice40/pack_tests/place_constr.v b/ice40/pack_tests/place_constr.v
new file mode 100644
index 00000000..f915a203
--- /dev/null
+++ b/ice40/pack_tests/place_constr.v
@@ -0,0 +1,54 @@
+module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
+
+wire temp0, temp1;
+
+(* BEL="1_1_lc0" *)
+SB_LUT4 #(
+    .LUT_INIT(2'b01)
+) lut0 (
+    .I3(),
+    .I2(),
+    .I1(),
+    .I0(ina),
+    .O(temp0)
+);
+
+
+(* BEL="1_3_lc0" *)
+SB_LUT4 #(
+    .LUT_INIT(2'b01)
+) lut1 (
+    .I3(),
+    .I2(),
+    .I1(),
+    .I0(inb),
+    .O(temp1)
+);
+
+(* BEL="1_1_lc0" *)
+SB_DFF ff0 (
+    .C(clk),
+    .D(temp1),
+    .Q(outa)
+);
+
+
+(* BEL="1_1_lc7" *)
+SB_DFF ff1 (
+    .C(clk),
+    .D(inb),
+    .Q(outb)
+);
+
+
+(* BEL="1_6_lc7" *)
+SB_DFF ff2 (
+    .C(clk),
+    .D(temp1),
+    .Q(outc)
+);
+
+
+assign outd = 1'b0;
+
+endmodule
diff --git a/ice40/pack_tests/test.sh b/ice40/pack_tests/test.sh
index 88ff5b1d..dd1f345c 100755
--- a/ice40/pack_tests/test.sh
+++ b/ice40/pack_tests/test.sh
@@ -5,7 +5,8 @@ yosys -p "synth_ice40 -nocarry -top io_wrapper; write_json ${NAME}.json" $1 io_w
 ../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc
 icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
 
-yosys -p "rename chip gate;\
+yosys -p "read_verilog +/ice40/cells_sim.v;\
+          rename chip gate;\
           read_verilog $1;\
           rename top gold;\
           hierarchy;\
-- 
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