From d13a84b6873ca3c177638ef077d8d315c57da1ca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Jun 2018 12:37:56 +0200 Subject: Add iCE40 blockram bels Signed-off-by: Clifford Wolf --- ice40/chip.cc | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) (limited to 'ice40/chip.cc') diff --git a/ice40/chip.cc b/ice40/chip.cc index cd427377..824829e5 100644 --- a/ice40/chip.cc +++ b/ice40/chip.cc @@ -25,6 +25,8 @@ IdString belTypeToId(BelType type) { if (type == TYPE_ICESTORM_LC) return "ICESTORM_LC"; + if (type == TYPE_ICESTORM_RAM) + return "ICESTORM_RAM"; if (type == TYPE_SB_IO) return "SB_IO"; return IdString(); @@ -34,6 +36,8 @@ BelType belTypeFromId(IdString id) { if (id == "ICESTORM_LC") return TYPE_ICESTORM_LC; + if (id == "ICESTORM_RAM") + return TYPE_ICESTORM_RAM; if (id == "SB_IO") return TYPE_SB_IO; return TYPE_NIL; @@ -57,6 +61,89 @@ IdString PortPinToId(PortPin type) X(CLK) X(SR) + X(MASK_0) + X(MASK_1) + X(MASK_2) + X(MASK_3) + X(MASK_4) + X(MASK_5) + X(MASK_6) + X(MASK_7) + X(MASK_8) + X(MASK_9) + X(MASK_10) + X(MASK_11) + X(MASK_12) + X(MASK_13) + X(MASK_14) + X(MASK_15) + + X(RDATA_0) + X(RDATA_1) + X(RDATA_2) + X(RDATA_3) + X(RDATA_4) + X(RDATA_5) + X(RDATA_6) + X(RDATA_7) + X(RDATA_8) + X(RDATA_9) + X(RDATA_10) + X(RDATA_11) + X(RDATA_12) + X(RDATA_13) + X(RDATA_14) + X(RDATA_15) + + X(WDATA_0) + X(WDATA_1) + X(WDATA_2) + X(WDATA_3) + X(WDATA_4) + X(WDATA_5) + X(WDATA_6) + X(WDATA_7) + X(WDATA_8) + X(WDATA_9) + X(WDATA_10) + X(WDATA_11) + X(WDATA_12) + X(WDATA_13) + X(WDATA_14) + X(WDATA_15) + + X(WADDR_0) + X(WADDR_1) + X(WADDR_2) + X(WADDR_3) + X(WADDR_4) + X(WADDR_5) + X(WADDR_6) + X(WADDR_7) + X(WADDR_8) + X(WADDR_9) + X(WADDR_10) + + X(RADDR_0) + X(RADDR_1) + X(RADDR_2) + X(RADDR_3) + X(RADDR_4) + X(RADDR_5) + X(RADDR_6) + X(RADDR_7) + X(RADDR_8) + X(RADDR_9) + X(RADDR_10) + + X(WCLK) + X(WCLKE) + X(WE) + + X(RCLK) + X(RCLKE) + X(RE) + X(PACKAGE_PIN) X(LATCH_INPUT_VALUE) X(CLOCK_ENABLE) @@ -88,6 +175,89 @@ PortPin PortPinFromId(IdString id) X(CLK) X(SR) + X(MASK_0) + X(MASK_1) + X(MASK_2) + X(MASK_3) + X(MASK_4) + X(MASK_5) + X(MASK_6) + X(MASK_7) + X(MASK_8) + X(MASK_9) + X(MASK_10) + X(MASK_11) + X(MASK_12) + X(MASK_13) + X(MASK_14) + X(MASK_15) + + X(RDATA_0) + X(RDATA_1) + X(RDATA_2) + X(RDATA_3) + X(RDATA_4) + X(RDATA_5) + X(RDATA_6) + X(RDATA_7) + X(RDATA_8) + X(RDATA_9) + X(RDATA_10) + X(RDATA_11) + X(RDATA_12) + X(RDATA_13) + X(RDATA_14) + X(RDATA_15) + + X(WDATA_0) + X(WDATA_1) + X(WDATA_2) + X(WDATA_3) + X(WDATA_4) + X(WDATA_5) + X(WDATA_6) + X(WDATA_7) + X(WDATA_8) + X(WDATA_9) + X(WDATA_10) + X(WDATA_11) + X(WDATA_12) + X(WDATA_13) + X(WDATA_14) + X(WDATA_15) + + X(WADDR_0) + X(WADDR_1) + X(WADDR_2) + X(WADDR_3) + X(WADDR_4) + X(WADDR_5) + X(WADDR_6) + X(WADDR_7) + X(WADDR_8) + X(WADDR_9) + X(WADDR_10) + + X(RADDR_0) + X(RADDR_1) + X(RADDR_2) + X(RADDR_3) + X(RADDR_4) + X(RADDR_5) + X(RADDR_6) + X(RADDR_7) + X(RADDR_8) + X(RADDR_9) + X(RADDR_10) + + X(WCLK) + X(WCLKE) + X(WE) + + X(RCLK) + X(RCLKE) + X(RE) + X(PACKAGE_PIN) X(LATCH_INPUT_VALUE) X(CLOCK_ENABLE) -- cgit v1.2.3