From 7aab4925b4573613e9b39c4f141c3e3f1a9e6f57 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 5 Aug 2018 22:31:59 -0700 Subject: Change getBudgetOverride() signature to return bool and modify budget in place --- ice40/arch.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 0b168383..b8bb13ea 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -637,17 +637,19 @@ std::vector Arch::getGroupGroups(GroupId group) const // ----------------------------------------------------------------------- -delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const +bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { const auto &driver = net_info->driver; if (driver.port == id_cout) { auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); if (driver_loc.y == sink_loc.y) - return 0; - return 250; + budget = 0; + else + budget = 190; + return true; } - return budget; + return false; } // ----------------------------------------------------------------------- -- cgit v1.2.3 From 21cd1d7dd6c1d033c933006a96b5eebfef220a9d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Aug 2018 12:11:47 -0700 Subject: Add new Arch::isIOCell() API function --- ice40/arch.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 1e7a383b..b142ae8b 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -898,6 +898,11 @@ bool Arch::isGlobalNet(const NetInfo *net) const return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out; } +bool Arch::isIOCell(const CellInfo *cell) const +{ + return cell->type == id_sb_io; +} + // Assign arch arg info void Arch::assignArchInfo() { -- cgit v1.2.3 From f44a5fb904e6e52e8383e8f13d9b3f4ab9d7ce48 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Aug 2018 17:35:23 -0700 Subject: clangformat --- ice40/arch.cc | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 324934d0..16104033 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -291,7 +291,8 @@ BelId Arch::getBelByLocation(Loc loc) const BelRange Arch::getBelsByTile(int x, int y) const { - // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used + // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates + // are used BelRange br; br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index; @@ -645,23 +646,27 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay auto sink_loc = getBelLocation(sink.cell->bel); if (driver_loc.y == sink_loc.y) budget = 0; - else switch (args.type) { + else + switch (args.type) { #ifndef ICE40_HX1K_ONLY case ArchArgs::HX8K: #endif case ArchArgs::HX1K: - budget = 190; break; + budget = 190; + break; #ifndef ICE40_HX1K_ONLY case ArchArgs::LP384: case ArchArgs::LP1K: case ArchArgs::LP8K: - budget = 290; break; + budget = 290; + break; case ArchArgs::UP5K: - budget = 560; break; + budget = 560; + break; #endif default: log_error("Unsupported iCE40 chip type.\n"); - } + } return true; } return false; @@ -913,10 +918,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out; } -bool Arch::isIOCell(const CellInfo *cell) const -{ - return cell->type == id_sb_io; -} +bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id_sb_io; } // Assign arch arg info void Arch::assignArchInfo() -- cgit v1.2.3 From bf42e525cb7ab6ae071b16dfeca55194878be69c Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 14:37:59 +0200 Subject: Arch API: New specification for timing port classes Signed-off-by: David Shah --- ice40/arch.cc | 68 +++++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 50 insertions(+), 18 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 16104033..0f81bfea 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -27,6 +27,7 @@ #include "placer1.h" #include "router1.h" #include "util.h" + NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- @@ -106,7 +107,9 @@ BelType Arch::belTypeFromId(IdString type) const void IdString::initialize_arch(const BaseCtx *ctx) { #define X(t) initialize_add(ctx, #t, PIN_##t); + #include "portpins.inc" + #undef X } @@ -888,27 +891,56 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return false; } -IdString Arch::getPortClock(const CellInfo *cell, IdString port) const +// Get the port class, also setting clockPort to associated clock if applicable +TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const { - if (cell->type == id_icestorm_lc && cell->lcInfo.dffEnable) { - if (port != id_lo && port != id_cin && port != id_cout) - return id_clk; - } else if (cell->type == id_icestorm_ram) { - if (port.str(this)[0] == 'R') - return id_rclk; + if (cell->type == id_icestorm_lc) { + if (port == id_clk) + return TMG_CLOCK_INPUT; + if (port == id_cin) + return TMG_COMB_INPUT; + if (port == id_cout || port == id_lo) + return TMG_COMB_OUTPUT; + if (cell->lcInfo.dffEnable) { + clockPort = id_clk; + if (port == id_o) + return TMG_REGISTER_OUTPUT; + else + return TMG_REGISTER_INPUT; + } else { + if (port == id_o) + return TMG_COMB_OUTPUT; + else + return TMG_COMB_INPUT; + } + } else if (cell->type == id_icestorm_ram || cell->type == id("ICESTORM_DSP") || + cell->type == id("ICESTORM_SPRAM")) { + if (port == id_clk) + return TMG_CLOCK_INPUT; + else if (cell->ports.at(port).type == PORT_OUT) + return TMG_REGISTER_OUTPUT; else - return id_wclk; + return TMG_REGISTER_INPUT; + } else if (cell->type == id_sb_io) { + if (port == id("D_IN_0") || port == id("D_IN_1")) + return TMG_STARTPOINT; + if (port == id("D_OUT_0") || port == id("D_OUT_1")) + return TMG_STARTPOINT; + return TMG_IGNORE; + } else if (cell->type == id("ICESTORM_PLL")) { + if (port == id("PLLOUT_A") || port == id("PLLOUT_B")) + return TMG_GEN_CLOCK; + return TMG_IGNORE; + } else if (cell->type == id("ICESTORM_LFOSC")) { + if (port == id("CLKLF")) + return TMG_GEN_CLOCK; + return TMG_IGNORE; + } else if (cell->type == id("ICESTORM_HFOSC")) { + if (port == id("CLKHF")) + return TMG_GEN_CLOCK; + return TMG_IGNORE; } - return IdString(); -} - -bool Arch::isClockPort(const CellInfo *cell, IdString port) const -{ - if (cell->type == id("ICESTORM_LC") && port == id("CLK")) - return true; - if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK")))) - return true; - return false; + return TMG_IGNORE; } bool Arch::isGlobalNet(const NetInfo *net) const -- cgit v1.2.3 From d8b383003194f45cae8486905e50575d792a4640 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 14:58:43 +0200 Subject: timing: Update to new use API (currently broken) Signed-off-by: David Shah --- ice40/arch.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 0f81bfea..fddfabfd 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -915,7 +915,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id } } else if (cell->type == id_icestorm_ram || cell->type == id("ICESTORM_DSP") || cell->type == id("ICESTORM_SPRAM")) { - if (port == id_clk) + if (port == id_clk || port == id_rclk || port == id_wclk) return TMG_CLOCK_INPUT; else if (cell->ports.at(port).type == PORT_OUT) return TMG_REGISTER_OUTPUT; @@ -925,7 +925,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id if (port == id("D_IN_0") || port == id("D_IN_1")) return TMG_STARTPOINT; if (port == id("D_OUT_0") || port == id("D_OUT_1")) - return TMG_STARTPOINT; + return TMG_ENDPOINT; return TMG_IGNORE; } else if (cell->type == id("ICESTORM_PLL")) { if (port == id("PLLOUT_A") || port == id("PLLOUT_B")) -- cgit v1.2.3 From 787fe5661cedf42a55f6aeb285d164e6cdf56404 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 15:00:39 +0200 Subject: ice40: Timing arch fix Signed-off-by: David Shah --- ice40/arch.cc | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index fddfabfd..bfab91a1 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -913,9 +913,23 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id else return TMG_COMB_INPUT; } - } else if (cell->type == id_icestorm_ram || cell->type == id("ICESTORM_DSP") || - cell->type == id("ICESTORM_SPRAM")) { - if (port == id_clk || port == id_rclk || port == id_wclk) + } else if (cell->type == id_icestorm_ram) { + + if (port == id_rclk || port == id_wclk) + return TMG_CLOCK_INPUT; + + if (port.str(this)[0] == 'R') + clockPort = id_rclk; + else + clockPort = id_wclk; + + if (cell->ports.at(port).type == PORT_OUT) + return TMG_REGISTER_OUTPUT; + else + return TMG_REGISTER_INPUT; + } else if (cell->type == id("ICESTORM_DSP") || cell->type == id("ICESTORM_SPRAM")) { + clockPort = id_clk; + if (port == id_clk) return TMG_CLOCK_INPUT; else if (cell->ports.at(port).type == PORT_OUT) return TMG_REGISTER_OUTPUT; -- cgit v1.2.3 From d173ddba367f7082f122df75dffb59577afaf0b4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 15:07:41 +0200 Subject: timing: Debugging implementation of new timing API Signed-off-by: David Shah --- ice40/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index bfab91a1..abce0aba 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -938,7 +938,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id } else if (cell->type == id_sb_io) { if (port == id("D_IN_0") || port == id("D_IN_1")) return TMG_STARTPOINT; - if (port == id("D_OUT_0") || port == id("D_OUT_1")) + if (port == id("D_OUT_0") || port == id("D_OUT_1") || port == id("OUTPUT_ENABLE")) return TMG_ENDPOINT; return TMG_IGNORE; } else if (cell->type == id("ICESTORM_PLL")) { -- cgit v1.2.3 From e6eb2038683fd3c81570b8c8e5307678bca5f77e Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 16:34:41 +0200 Subject: ice40: Add timing arcs through global buffers Signed-off-by: David Shah --- ice40/arch.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index abce0aba..3d31f980 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -953,6 +953,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id if (port == id("CLKHF")) return TMG_GEN_CLOCK; return TMG_IGNORE; + } else if (cell->type == id_sb_gb) { + if (port == id_glb_buf_out) + return TMG_COMB_OUTPUT; + return TMG_COMB_INPUT; } return TMG_IGNORE; } -- cgit v1.2.3 From 433ad6462e401e722fbdd033c2b4b1c9a3537947 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 17:06:59 +0200 Subject: Arch API: Removing Arch::isIOCell Signed-off-by: David Shah --- ice40/arch.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 3d31f980..888a0dee 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -968,8 +968,6 @@ bool Arch::isGlobalNet(const NetInfo *net) const return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out; } -bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id_sb_io; } - // Assign arch arg info void Arch::assignArchInfo() { -- cgit v1.2.3 From 751335977fe7d69b23f6110ec4938408ec7a7ff8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 18:07:34 +0200 Subject: ice40: Add error for unknown cell type when getting timing info Signed-off-by: David Shah --- ice40/arch.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 888a0dee..5e56ea10 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -957,8 +957,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id if (port == id_glb_buf_out) return TMG_COMB_OUTPUT; return TMG_COMB_INPUT; + } else if (cell->type == id("SB_WARMBOOT")) { + return TMG_ENDPOINT; } - return TMG_IGNORE; + log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this)); } bool Arch::isGlobalNet(const NetInfo *net) const -- cgit v1.2.3