From 7858663aa7f211cebde2d543f7d0094d84ca11b1 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 11:46:14 +0200 Subject: timing: Model clock to Q times Signed-off-by: David Shah --- ice40/arch.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index 65b21afd..c29673cc 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -733,6 +733,14 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort } else if (fromPort == id("I2") && toPort == id("COUT")) { delay = 230; return true; + } else if (fromPort == id("CLK") && toPort == id("O")) { + delay = 540; + return true; + } + } else if (cell->type == id("ICESTORM_RAM")) { + if (fromPort == id("RCLK")) { + delay = 2140; + return true; } } return false; @@ -743,6 +751,11 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) { if (port != id("LO") && port != id("CIN") && port != id("COUT")) return id("CLK"); + } else if (cell->type == id("ICESTORM_RAM")) { + if (port.str(this)[0] == 'R') + return id("RCLK"); + else + return id("WCLK"); } return IdString(); } @@ -751,6 +764,8 @@ bool Arch::isClockPort(const CellInfo *cell, IdString port) const { if (cell->type == id("ICESTORM_LC") && port == id("CLK")) return true; + if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK")))) + return true; return false; } -- cgit v1.2.3