From 6a32aca4ac8705b637943c236cedd2f36422fb21 Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 18 Feb 2022 10:52:37 +0000 Subject: refactor: New member functions to replace design_utils Signed-off-by: gatecat --- gowin/arch.cc | 6 +++--- gowin/cells.cc | 38 ++++++++++++++++----------------- gowin/pack.cc | 66 +++++++++++++++++++++++++++++----------------------------- 3 files changed, 55 insertions(+), 55 deletions(-) (limited to 'gowin') diff --git a/gowin/arch.cc b/gowin/arch.cc index b104013d..af851467 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -1600,9 +1600,9 @@ void Arch::assignArchInfo() ci->is_slice = true; ci->ff_used = ci->params.at(id_FF_USED).as_bool(); ci->ff_type = id(ci->params.at(id_FF_TYPE).as_string()); - ci->slice_clk = get_net_or_empty(ci, id_CLK); - ci->slice_ce = get_net_or_empty(ci, id_CE); - ci->slice_lsr = get_net_or_empty(ci, id_LSR); + ci->slice_clk = ci->getPort(id_CLK); + ci->slice_ce = ci->getPort(id_CE); + ci->slice_lsr = ci->getPort(id_LSR); // add timing paths addCellTimingClock(cname, id_CLK); diff --git a/gowin/cells.cc b/gowin/cells.cc index aef34f53..d862458c 100644 --- a/gowin/cells.cc +++ b/gowin/cells.cc @@ -93,12 +93,12 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) IdString sim_names[4] = {id_I0, id_I1, id_I2, id_I3}; IdString wire_names[4] = {id_A, id_B, id_C, id_D}; for (int i = 0; i < 4; i++) { - replace_port(lut, sim_names[i], lc, wire_names[i]); + lut->movePortTo(sim_names[i], lc, wire_names[i]); } if (no_dff) { lc->params[id_FF_USED] = 0; - replace_port(lut, id_F, lc, id_F); + lut->movePortTo(id_F, lc, id_F); } } @@ -106,12 +106,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l { lc->params[id_FF_USED] = 1; lc->params[id_FF_TYPE] = dff->type.str(ctx); - replace_port(dff, id_CLK, lc, id_CLK); - replace_port(dff, id_CE, lc, id_CE); - replace_port(dff, id_SET, lc, id_LSR); - replace_port(dff, id_RESET, lc, id_LSR); - replace_port(dff, id_CLEAR, lc, id_LSR); - replace_port(dff, id_PRESET, lc, id_LSR); + dff->movePortTo(id_CLK, lc, id_CLK); + dff->movePortTo(id_CE, lc, id_CE); + dff->movePortTo(id_SET, lc, id_LSR); + dff->movePortTo(id_RESET, lc, id_LSR); + dff->movePortTo(id_CLEAR, lc, id_LSR); + dff->movePortTo(id_PRESET, lc, id_LSR); if (pass_thru_lut) { // Fill LUT with alternating 10 const int init_size = 1 << 4; @@ -121,10 +121,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l init.append("10"); lc->params[id_INIT] = Property::from_string(init); - replace_port(dff, id_D, lc, id_A); + dff->movePortTo(id_D, lc, id_A); } - replace_port(dff, id_Q, lc, id_Q); + dff->movePortTo(id_Q, lc, id_Q); } void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool &todelete_cells) @@ -132,29 +132,29 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool &to if (nxio->type == id_IBUF) { if (iob->type == id_IOBS) { // VCC -> OEN - connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), iob, id_OEN); + iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); } iob->params[id_INPUT_USED] = 1; - replace_port(nxio, id_O, iob, id_O); + nxio->movePortTo(id_O, iob, id_O); } else if (nxio->type == id_OBUF) { if (iob->type == id_IOBS) { // VSS -> OEN - connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), iob, id_OEN); + iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_GND_NET")].get()); } iob->params[id_OUTPUT_USED] = 1; - replace_port(nxio, id_I, iob, id_I); + nxio->movePortTo(id_I, iob, id_I); } else if (nxio->type == id_TBUF) { iob->params[id_ENABLE_USED] = 1; iob->params[id_OUTPUT_USED] = 1; - replace_port(nxio, id_I, iob, id_I); - replace_port(nxio, id_OEN, iob, id_OEN); + nxio->movePortTo(id_I, iob, id_I); + nxio->movePortTo(id_OEN, iob, id_OEN); } else if (nxio->type == id_IOBUF) { iob->params[id_ENABLE_USED] = 1; iob->params[id_INPUT_USED] = 1; iob->params[id_OUTPUT_USED] = 1; - replace_port(nxio, id_I, iob, id_I); - replace_port(nxio, id_O, iob, id_O); - replace_port(nxio, id_OEN, iob, id_OEN); + nxio->movePortTo(id_I, iob, id_I); + nxio->movePortTo(id_O, iob, id_O); + nxio->movePortTo(id_OEN, iob, id_OEN); } else { NPNR_ASSERT(false); } diff --git a/gowin/pack.cc b/gowin/pack.cc index 1201e310..268f26ef 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -96,7 +96,7 @@ static void pack_alus(Context *ctx) log_info("packed ALU head into %s. CIN net is %s\n", ctx->nameOf(packed_head.get()), ctx->nameOf(cin_netId)); } - connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed_head.get(), id_C); + packed_head->connectPort(id_C, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); if (cin_netId == ctx->id("$PACKER_GND_NET")) { // CIN = 0 packed_head->params[id_ALU_MODE] = std::string("C2L"); @@ -106,8 +106,8 @@ static void pack_alus(Context *ctx) packed_head->params[id_ALU_MODE] = std::string("ONE2C"); } else { // CIN from logic - connect_port(ctx, ctx->nets[cin_netId].get(), packed_head.get(), id_B); - connect_port(ctx, ctx->nets[cin_netId].get(), packed_head.get(), id_D); + packed_head->connectPort(id_B, ctx->nets[cin_netId].get()); + packed_head->connectPort(id_D, ctx->nets[cin_netId].get()); packed_head->params[id_ALU_MODE] = std::string("0"); // ADD } } @@ -123,9 +123,9 @@ static void pack_alus(Context *ctx) packed_cells.insert(ci->name); // CIN/COUT are hardwired, delete - disconnect_port(ctx, ci, id_CIN); + ci->disconnectPort(id_CIN); NetInfo *cout = ci->ports.at(id_COUT).net; - disconnect_port(ctx, ci, id_COUT); + ci->disconnectPort(id_COUT); std::unique_ptr packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_ALULC"); if (ctx->verbose) { @@ -135,9 +135,9 @@ static void pack_alus(Context *ctx) int mode = int_or_default(ci->params, id_ALU_MODE); packed->params[id_ALU_MODE] = mode; if (mode == 9) { // MULT - connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), packed.get(), id_C); + packed->connectPort(id_C, ctx->nets[ctx->id("$PACKER_GND_NET")].get()); } else { - connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed.get(), id_C); + packed->connectPort(id_C, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); } // add to cluster @@ -149,30 +149,30 @@ static void pack_alus(Context *ctx) ++alu_idx; // connect all remainig ports - replace_port(ci, id_SUM, packed.get(), id_F); + ci->movePortTo(id_SUM, packed.get(), id_F); switch (mode) { case 0: // ADD - replace_port(ci, id_I0, packed.get(), id_B); - replace_port(ci, id_I1, packed.get(), id_D); + ci->movePortTo(id_I0, packed.get(), id_B); + ci->movePortTo(id_I1, packed.get(), id_D); break; case 1: // SUB - replace_port(ci, id_I0, packed.get(), id_A); - replace_port(ci, id_I1, packed.get(), id_D); + ci->movePortTo(id_I0, packed.get(), id_A); + ci->movePortTo(id_I1, packed.get(), id_D); break; case 5: // LE - replace_port(ci, id_I0, packed.get(), id_A); - replace_port(ci, id_I1, packed.get(), id_B); + ci->movePortTo(id_I0, packed.get(), id_A); + ci->movePortTo(id_I1, packed.get(), id_B); break; case 9: // MULT - replace_port(ci, id_I0, packed.get(), id_A); - replace_port(ci, id_I1, packed.get(), id_B); - disconnect_port(ctx, packed.get(), id_D); - connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed.get(), id_D); + ci->movePortTo(id_I0, packed.get(), id_A); + ci->movePortTo(id_I1, packed.get(), id_B); + packed->disconnectPort(id_D); + packed->connectPort(id_D, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); break; default: - replace_port(ci, id_I0, packed.get(), id_A); - replace_port(ci, id_I1, packed.get(), id_B); - replace_port(ci, id_I3, packed.get(), id_D); + ci->movePortTo(id_I0, packed.get(), id_A); + ci->movePortTo(id_I1, packed.get(), id_B); + ci->movePortTo(id_I3, packed.get(), id_D); } new_cells.push_back(std::move(packed)); @@ -191,7 +191,7 @@ static void pack_alus(Context *ctx) ctx->nameOf(cout)); } packed_tail->params[id_ALU_MODE] = std::string("C2L"); - connect_port(ctx, cout, packed_tail.get(), id_F); + packed_tail->connectPort(id_F, cout); // add to cluster packed_tail->cluster = packed_head->name; packed_tail->constr_z = alu_idx % 6; @@ -275,8 +275,8 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool &packed_ce packed->constr_children.clear(); // reconnect MUX ports - replace_port(ci, id_O, packed.get(), id_OF); - replace_port(ci, id_I1, packed.get(), id_I1); + ci->movePortTo(id_O, packed.get(), id_OF); + ci->movePortTo(id_I1, packed.get(), id_I1); // remove cells packed_cells.insert(ci->name); @@ -320,10 +320,10 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool &packed_ce packed->constr_children.clear(); // reconnect MUX ports - replace_port(ci, id_O, packed.get(), id_OF); - replace_port(ci, id_S0, packed.get(), id_SEL); - replace_port(ci, id_I0, packed.get(), id_I0); - replace_port(ci, id_I1, packed.get(), id_I1); + ci->movePortTo(id_O, packed.get(), id_OF); + ci->movePortTo(id_S0, packed.get(), id_SEL); + ci->movePortTo(id_I0, packed.get(), id_I0); + ci->movePortTo(id_I1, packed.get(), id_I1); // remove cells packed_cells.insert(ci->name); @@ -394,10 +394,10 @@ static void pack_mux2_lut(Context *ctx, CellInfo *ci, bool (*pred)(const BaseCtx packed->constr_children.push_back(mux1); // reconnect MUX ports - replace_port(ci, id_O, packed.get(), id_OF); - replace_port(ci, id_S0, packed.get(), id_SEL); - replace_port(ci, id_I0, packed.get(), id_I0); - replace_port(ci, id_I1, packed.get(), id_I1); + ci->movePortTo(id_O, packed.get(), id_OF); + ci->movePortTo(id_S0, packed.get(), id_SEL); + ci->movePortTo(id_I0, packed.get(), id_I0); + ci->movePortTo(id_I1, packed.get(), id_I1); // remove cells packed_cells.insert(ci->name); @@ -711,7 +711,7 @@ static void pack_io(Context *ctx) // delete the $nexpnr_[io]buf for (auto &p : iob->ports) { IdString netname = p.second.net->name; - disconnect_port(ctx, iob, p.first); + iob->disconnectPort(p.first); delete_nets.insert(netname); } packed_cells.insert(iob->name); -- cgit v1.2.3