From 490dddf636bc50945ee6e6858f7c1942faa3aaf5 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Sun, 5 Jun 2022 16:59:06 +0200 Subject: WIP shadowram --- gowin/cells.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'gowin/cells.h') diff --git a/gowin/cells.h b/gowin/cells.h index 8f0636b8..b6d86497 100644 --- a/gowin/cells.h +++ b/gowin/cells.h @@ -111,6 +111,8 @@ inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SLICE; } +inline bool is_sram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_RAM16SDP4; } + // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports // as needed. Set no_dff if a DFF is not being used, so that the output // can be reconnected @@ -125,6 +127,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l // Convert a Gowin IO buffer to a IOB bel void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool &todelete_cells); +// Convert RAM16 to write port +void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw); + +// Convert RAM16 to slice +void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index); + NEXTPNR_NAMESPACE_END #endif -- cgit v1.2.3