From 2d45d57b3246814ad20988c6ecf941180faf58a6 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Thu, 26 Jan 2023 20:26:05 +1000 Subject: gowin: Add PLL support for the GW1NR-9C chip This chip is used in the Tangnano9k board. * all parameters of the rPLL primitive are supported; * all PLL outputs are treated as clock sources and optimized routing is applied to them; * primitive rPLL on different chips has a completely different structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C as many as four, despite this unification was carried out and different chips are processed by the same functions, but this led to the fact that you can not use the PLL chip GW1N-1 with the old apicula bases - will issue a warning and refuse to encode primitive. In other cases compatibility is supported. * Cosmetic change: the usage report shows the rPLL names without any service bels. * I use ctx->idf() on occasion, it's not a total redesign. Signed-off-by: YRabbit --- gowin/arch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gowin/arch.h') diff --git a/gowin/arch.h b/gowin/arch.h index 0dd5a62b..f060165a 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -478,8 +478,8 @@ struct Arch : BaseArch void pre_route(Context *ctx); void post_route(Context *ctx); void auto_longwires(); - void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col); void add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col); + void add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col); void fix_pll_nets(Context *ctx); bool is_GCLKT_iob(const CellInfo *cell); -- cgit v1.2.3