From 6a1212a1e14d19bda114317e9f544b534cbf2841 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Mon, 30 Jan 2023 12:49:57 +1000 Subject: gowin: Add PLL support for the GW1NR-9 chip And also unified the fixing of PLL to bels: the point is that PLL being at a certain location has the possibility to use a direct implicit wire to the clock source, but once we decide to use this direct wire, the PLL can no longer be moved. Signed-off-by: YRabbit --- gowin/arch.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'gowin/arch.h') diff --git a/gowin/arch.h b/gowin/arch.h index f060165a..6f76d577 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -482,6 +482,7 @@ struct Arch : BaseArch void add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col); void fix_pll_nets(Context *ctx); bool is_GCLKT_iob(const CellInfo *cell); + void bind_pll_to_bel(CellInfo *ci, int loc); GowinGlobalRouter globals_router; void mark_gowin_globals(Context *ctx); @@ -530,6 +531,14 @@ enum }; } +namespace PLL { // fixed PLL locations +enum +{ + left = 0, + right = 1 +}; +} + NEXTPNR_NAMESPACE_END #endif /* GOWIN_ARCH_H */ -- cgit v1.2.3