From 579b98c5963c2b86d191d481a2147a663a8196dd Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 1 Jun 2021 16:51:18 +0100 Subject: Use hashlib for core netlist structures Signed-off-by: gatecat --- generic/arch.cc | 4 ++-- generic/arch_pybindings.cc | 6 +++--- generic/pack.cc | 25 ++++++++++++++----------- 3 files changed, 19 insertions(+), 16 deletions(-) (limited to 'generic') diff --git a/generic/arch.cc b/generic/arch.cc index a683e34e..eb43aa6f 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -553,8 +553,8 @@ bool Arch::place() std::string placer = str_or_default(settings, id("placer"), defaultPlacer); if (placer == "heap") { bool have_iobuf_or_constr = false; - for (auto cell : sorted(cells)) { - CellInfo *ci = cell.second; + for (auto &cell : cells) { + CellInfo *ci = cell.second.get(); if (ci->type == id("GENERIC_IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) { have_iobuf_or_constr = true; break; diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index 50544dc1..735c7e41 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -138,9 +138,9 @@ void arch_wrap_python(py::module &m) fn_wrapper_3a, conv_from_str, pass_through, pass_through>::def_wrap(ctx_cls, "DecalXY"); - typedef std::unordered_map> CellMap; - typedef std::unordered_map> NetMap; - typedef std::unordered_map HierarchyMap; + typedef dict> CellMap; + typedef dict> NetMap; + typedef dict HierarchyMap; readonly_wrapper>::def_wrap(ctx_cls, "cells"); diff --git a/generic/pack.cc b/generic/pack.cc index 6b984fef..a1c325f8 100644 --- a/generic/pack.cc +++ b/generic/pack.cc @@ -34,14 +34,15 @@ static void pack_lut_lutffs(Context *ctx) std::unordered_set packed_cells; std::vector> new_cells; - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (ctx->verbose) log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx)); if (is_lut(ctx, ci)) { std::unique_ptr packed = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_LC"); - std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); + for (auto &attr : ci->attrs) + packed->attrs[attr.first] = attr.second; packed_cells.insert(ci->name); if (ctx->verbose) log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); @@ -91,12 +92,13 @@ static void pack_nonlut_ffs(Context *ctx) std::unordered_set packed_cells; std::vector> new_cells; - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (is_ff(ctx, ci)) { std::unique_ptr packed = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_DFFLC"); - std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); + for (auto &attr : ci->attrs) + packed->attrs[attr.first] = attr.second; if (ctx->verbose) log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); packed_cells.insert(ci->name); @@ -158,8 +160,8 @@ static void pack_constants(Context *ctx) bool gnd_used = false, vcc_used = false; - for (auto net : sorted(ctx->nets)) { - NetInfo *ni = net.second; + for (auto &net : ctx->nets) { + NetInfo *ni = net.second.get(); if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) { IdString drv_cell = ni->driver.cell->name; set_net_constant(ctx, ni, gnd_net.get(), false); @@ -207,8 +209,8 @@ static void pack_io(Context *ctx) std::vector> new_cells; log_info("Packing IOs..\n"); - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (is_nextpnr_iob(ctx, ci)) { CellInfo *iob = nullptr; if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) { @@ -254,7 +256,8 @@ static void pack_io(Context *ctx) } packed_cells.insert(ci->name); if (iob != nullptr) - std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin())); + for (auto &attr : ci->attrs) + iob->attrs[attr.first] = attr.second; } } for (auto pcell : packed_cells) { -- cgit v1.2.3 From ecc19c2c083f7e3ed7da95557731ded803d2cb1d Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 2 Jun 2021 10:01:36 +0100 Subject: Using hashlib in arches Signed-off-by: gatecat --- generic/arch.h | 39 +++++++++++++-------------------------- generic/archdefs.h | 5 ++--- generic/cells.cc | 2 +- generic/cells.h | 2 +- generic/pack.cc | 9 ++++----- 5 files changed, 21 insertions(+), 36 deletions(-) (limited to 'generic') diff --git a/generic/arch.h b/generic/arch.h index 50d2731c..9b16d873 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -80,7 +80,7 @@ struct BelInfo IdString type; std::map attrs; CellInfo *bound_cell; - std::unordered_map pins; + dict pins; DecalXY decalxy; int x, y, z; bool gb; @@ -101,27 +101,14 @@ struct CellDelayKey { IdString from, to; inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; } + unsigned int hash() const { return mkhash(from.hash(), to.hash()); } }; -NEXTPNR_NAMESPACE_END -namespace std { -template <> struct hash -{ - std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept - { - std::size_t seed = std::hash()(dk.from); - seed ^= std::hash()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2); - return seed; - } -}; -} // namespace std -NEXTPNR_NAMESPACE_BEGIN - struct CellTiming { - std::unordered_map portClasses; - std::unordered_map combDelays; - std::unordered_map> clockingInfo; + dict portClasses; + dict combDelays; + dict> clockingInfo; }; struct ArchRanges @@ -160,10 +147,10 @@ struct Arch : ArchAPI { std::string chipName; - std::unordered_map wires; - std::unordered_map pips; - std::unordered_map bels; - std::unordered_map groups; + dict wires; + dict pips; + dict bels; + dict groups; // These functions include useful errors if not found WireInfo &wire_info(IdStringList wire); @@ -172,16 +159,16 @@ struct Arch : ArchAPI std::vector bel_ids, wire_ids, pip_ids; - std::unordered_map bel_by_loc; + dict bel_by_loc; std::vector>> bels_by_tile; - std::unordered_map> decal_graphics; + dict> decal_graphics; int gridDimX, gridDimY; std::vector> tileBelDimZ; std::vector> tilePipDimZ; - std::unordered_map cellTiming; + dict cellTiming; void addWire(IdStringList name, IdString type, int x, int y); void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc); @@ -318,7 +305,7 @@ struct Arch : ArchAPI std::vector getCellTypes() const override { - std::unordered_set cell_types; + pool cell_types; for (auto bel : bels) { cell_types.insert(bel.second.type); } diff --git a/generic/archdefs.h b/generic/archdefs.h index 0489ab04..06680cc1 100644 --- a/generic/archdefs.h +++ b/generic/archdefs.h @@ -20,8 +20,7 @@ #ifndef GENERIC_ARCHDEFS_H #define GENERIC_ARCHDEFS_H -#include - +#include "hashlib.h" #include "idstringlist.h" NEXTPNR_NAMESPACE_BEGIN @@ -52,7 +51,7 @@ struct ArchCellInfo // Only packing rule for slice type primitives is a single clock per tile const NetInfo *slice_clk; // Cell to bel pin mapping - std::unordered_map> bel_pins; + dict> bel_pins; }; NEXTPNR_NAMESPACE_END diff --git a/generic/cells.cc b/generic/cells.cc index c4421f90..e1892353 100644 --- a/generic/cells.cc +++ b/generic/cells.cc @@ -106,7 +106,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l replace_port(dff, ctx->id("Q"), lc, ctx->id("Q")); } -void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set &todelete_cells) +void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool &todelete_cells) { if (nxio->type == ctx->id("$nextpnr_ibuf")) { iob->params[ctx->id("INPUT_USED")] = 1; diff --git a/generic/cells.h b/generic/cells.h index 646d738d..7a8443c5 100644 --- a/generic/cells.h +++ b/generic/cells.h @@ -48,7 +48,7 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = tr void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false); // Convert a nextpnr IO buffer to a GENERIC_IOB -void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set &todelete_cells); +void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool &todelete_cells); NEXTPNR_NAMESPACE_END diff --git a/generic/pack.cc b/generic/pack.cc index a1c325f8..dba86cce 100644 --- a/generic/pack.cc +++ b/generic/pack.cc @@ -19,7 +19,6 @@ #include #include -#include #include "cells.h" #include "design_utils.h" #include "log.h" @@ -32,7 +31,7 @@ static void pack_lut_lutffs(Context *ctx) { log_info("Packing LUT-FFs..\n"); - std::unordered_set packed_cells; + pool packed_cells; std::vector> new_cells; for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); @@ -89,7 +88,7 @@ static void pack_nonlut_ffs(Context *ctx) { log_info("Packing non-LUT FFs..\n"); - std::unordered_set packed_cells; + pool packed_cells; std::vector> new_cells; for (auto &cell : ctx->cells) { @@ -203,8 +202,8 @@ static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return ce // Pack IO buffers static void pack_io(Context *ctx) { - std::unordered_set packed_cells; - std::unordered_set delete_nets; + pool packed_cells; + pool delete_nets; std::vector> new_cells; log_info("Packing IOs..\n"); -- cgit v1.2.3 From eca1a4cee4f310c7e2c1216bd678143c1967edd4 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 2 Jun 2021 11:36:56 +0100 Subject: Use hashlib in most remaining code Signed-off-by: gatecat --- generic/main.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'generic') diff --git a/generic/main.cc b/generic/main.cc index 784178c6..2352b246 100644 --- a/generic/main.cc +++ b/generic/main.cc @@ -32,7 +32,7 @@ class GenericCommandHandler : public CommandHandler public: GenericCommandHandler(int argc, char **argv); virtual ~GenericCommandHandler(){}; - std::unique_ptr createContext(std::unordered_map &values) override; + std::unique_ptr createContext(dict &values) override; void setupArchContext(Context *ctx) override{}; void customBitstream(Context *ctx) override; @@ -52,7 +52,7 @@ po::options_description GenericCommandHandler::getArchOptions() void GenericCommandHandler::customBitstream(Context *ctx) {} -std::unique_ptr GenericCommandHandler::createContext(std::unordered_map &values) +std::unique_ptr GenericCommandHandler::createContext(dict &values) { ArchArgs chipArgs; if (values.find("arch.name") != values.end()) { -- cgit v1.2.3