From 0d41fff3a70a298036aa6fdc103093631998a2bd Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 1 Apr 2021 13:18:07 -0700 Subject: [interchange] Add crude pseudo pip model. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/luts.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'fpga_interchange/luts.h') diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h index 5a46b3ed..6978c7d2 100644 --- a/fpga_interchange/luts.h +++ b/fpga_interchange/luts.h @@ -92,8 +92,18 @@ struct LutMapper std::vector cells; bool remap_luts(const Context *ctx); + + // Determine which wires given the current mapping must be tied to the + // default constant. + // + // Returns a bit mask, 1 meaning it must be tied. Otherwise means that + // the pin is free to be a signal. uint32_t check_wires(const std::vector> &bel_to_cell_pin_remaps, const std::vector &lut_bels, uint32_t used_pins) const; + + // Version of check_wires that uses current state of cells based on pin + // mapping in cells variable. + uint32_t check_wires(const Context *ctx) const; }; // Rotate and merge a LUT equation into an array of levels. -- cgit v1.2.3 From 8773c645cae199d85d63461614c70854f54ae4db Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 1 Apr 2021 15:19:21 -0700 Subject: [interchange] Prevent site router from generating incorrect LUTs. The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/luts.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'fpga_interchange/luts.h') diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h index 6978c7d2..980fe530 100644 --- a/fpga_interchange/luts.h +++ b/fpga_interchange/luts.h @@ -27,6 +27,7 @@ #include "nextpnr_namespaces.h" #include "dynamic_bitarray.h" +#include "hash_table.h" NEXTPNR_NAMESPACE_BEGIN @@ -91,7 +92,7 @@ struct LutMapper std::vector cells; - bool remap_luts(const Context *ctx); + bool remap_luts(const Context *ctx, HashTables::HashSet *blocked_luts); // Determine which wires given the current mapping must be tied to the // default constant. @@ -99,7 +100,8 @@ struct LutMapper // Returns a bit mask, 1 meaning it must be tied. Otherwise means that // the pin is free to be a signal. uint32_t check_wires(const std::vector> &bel_to_cell_pin_remaps, - const std::vector &lut_bels, uint32_t used_pins) const; + const std::vector &lut_bels, uint32_t used_pins, + HashTables::HashSet *blocked_luts) const; // Version of check_wires that uses current state of cells based on pin // mapping in cells variable. -- cgit v1.2.3