From cc687b3b726d538be4a8dfa6cb8e1b4b96a837e2 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 16 Feb 2021 17:22:24 -0800 Subject: Change makefiles to build a FPGA interchange BBA. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/examples/archcheck/Makefile | 10 +-- fpga_interchange/examples/common.mk | 8 +++ fpga_interchange/examples/create_bba/Makefile | 90 +++++++++++++++++++++++++++ fpga_interchange/examples/template.mk | 14 +---- 4 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 fpga_interchange/examples/common.mk create mode 100644 fpga_interchange/examples/create_bba/Makefile (limited to 'fpga_interchange/examples') diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile index 8984e1b4..cf82013b 100644 --- a/fpga_interchange/examples/archcheck/Makefile +++ b/fpga_interchange/examples/archcheck/Makefile @@ -1,16 +1,16 @@ -NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr) -NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange -BBA_PATH := $(NEXTPNR_PATH)/build/test.bin +include ../common.mk PACKAGE := csg324 -.PHONY: +.PHONY: check check_test_data -check: +check: check_test_data $(NEXTPNR_BIN) \ --chipdb $(BBA_PATH) \ --package $(PACKAGE) \ --test + +check_test_data: $(NEXTPNR_BIN) \ --chipdb $(BBA_PATH) \ --run $(NEXTPNR_PATH)/python/check_arch_api.py diff --git a/fpga_interchange/examples/common.mk b/fpga_interchange/examples/common.mk new file mode 100644 index 00000000..8a8dc471 --- /dev/null +++ b/fpga_interchange/examples/common.mk @@ -0,0 +1,8 @@ +NEXTPNR_PATH := $(realpath ../../..) +NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange +BBA_PATH := $(realpath ..)/create_bba/build/test.bin + +RAPIDWRIGHT_PATH := $(realpath ..)/create_bba/build/RapidWright +INTERCHANGE_PATH := $(realpath ..)/create_bba/build/fpga-interchange-schema/interchange + +DEVICE := $(realpath ..)/create_bba/build/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile new file mode 100644 index 00000000..43f43a29 --- /dev/null +++ b/fpga_interchange/examples/create_bba/Makefile @@ -0,0 +1,90 @@ +# +# nextpnr -- Next Generation Place and Route +# +# Copyright (C) 2021 Symbiflow Authors +# +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + + +# This Makefile provides a streamlined way to create an example +# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts. +# +# FPGA interchange device database is generated via RapidWright. +# +# Currently FPGA interchange physical netlist (e.g. place and route route) to +# FASM support is not done, so bitstream generation relies on RapidWright to +# convert FPGA interchange logical and physical netlist into a Vivado DCP. + +include ../common.mk + +.DELETE_ON_ERROR: + +.PHONY: all chipdb + +all: chipdb + +build: + mkdir build + +build/RapidWright: | build + # FIXME: Update URL / branch as fixes are merged upstream and / or + # interchange branch on Xilinx/RapidWright is merged to master branch. + # + #cd build && git clone -b interchange https://github.com/Xilinx/RapidWright.git + cd build && git clone -b move_strlist https://github.com/litghost/RapidWright.git + +build/env: | build + python3 -mvenv build/env + +build/python-fpga-interchange: | build + cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git + +build/fpga-interchange-schema: | build + cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git + +build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright + source build/env/bin/activate && \ + cd build/python-fpga-interchange/ && \ + pip install -r requirements.txt + touch build/.setup + +$(NEXTPNR_PATH)/build: + mkdir $(NEXTPNR_PATH)/build + +$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build + $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange .. + make -j -C $(NEXTPNR_PATH)/build + +$(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup + source build/env/bin/activate && \ + cd build/python-fpga-interchange/ && \ + make \ + -f Makefile.rapidwright \ + NEXTPNR_PATH=$(NEXTPNR_PATH) \ + RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \ + INTERCHANGE_PATH=$(INTERCHANGE_PATH) + +$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba + $(NEXTPNR_PATH)/build/bba/bbasm -l $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba $(BBA_PATH) + +chipdb: $(BBA_PATH) + +test: chipdb + $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \ + --chipdb $(BBA_PATH) \ + --package csg324 \ + --test + +clean: + rm -rf build diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk index 11710058..8bdded3f 100644 --- a/fpga_interchange/examples/template.mk +++ b/fpga_interchange/examples/template.mk @@ -1,12 +1,4 @@ -NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr) -NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange -BBA_PATH := $(NEXTPNR_PATH)/build/test.bin - -RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright) - -INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange - -DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device) +include ../common.mk .DELETE_ON_ERROR: .PHONY: all debug clean @@ -39,7 +31,7 @@ build/$(DESIGN).phys: build/$(DESIGN).netlist --xdc $(DESIGN).xdc \ --netlist build/$(DESIGN).netlist \ --phys build/$(DESIGN).phys \ - --package $(PACKAGE) + --package $(PACKAGE) \ build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys /usr/bin/time -v python3 -mfpga_interchange.convert \ @@ -64,5 +56,5 @@ build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \ build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp -clean:: +clean: rm -rf build -- cgit v1.2.3