From 104536b7aae5970ae1d1e95394f26fbf04603d12 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 2 Jun 2021 09:49:30 +0200 Subject: interchange: add support for generating BEL clusters Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi --- fpga_interchange/examples/tests.cmake | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/examples') diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake index 3c97fe26..48b1cee3 100644 --- a/fpga_interchange/examples/tests.cmake +++ b/fpga_interchange/examples/tests.cmake @@ -77,13 +77,14 @@ function(add_interchange_test) # Synthesis set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json) + set(synth_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.json.log) add_custom_command( OUTPUT ${synth_json} COMMAND ${CMAKE_COMMAND} -E env SOURCES="${sources}" OUT_JSON=${synth_json} TECHMAP=${techmap} - yosys -c ${tcl} + yosys -c ${tcl} -l ${synth_log} DEPENDS ${sources} ${techmap} ${tcl} ) @@ -134,6 +135,7 @@ function(add_interchange_test) get_property(chipdb_bin_loc TARGET device-${device} PROPERTY CHIPDB_BIN_LOC) set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys) + set(phys_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.log) add_custom_command( OUTPUT ${phys} COMMAND @@ -143,6 +145,7 @@ function(add_interchange_test) --netlist ${netlist} --phys ${phys} --package ${package} + --log ${phys_log} DEPENDS nextpnr-fpga_interchange ${netlist} @@ -151,6 +154,7 @@ function(add_interchange_test) ${chipdb_bin_loc} ) + set(phys_verbose_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.verbose.log) add_custom_target( test-${family}-${name}-phys-verbose COMMAND @@ -161,6 +165,7 @@ function(add_interchange_test) --phys ${phys} --package ${package} --verbose + --log ${phys_verbose_log} DEPENDS ${netlist} ${xdc} -- cgit v1.2.3 From 490ca794c5a934c1a6aeaf681818a6c6d0c4e5e2 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Thu, 10 Jun 2021 12:41:47 +0200 Subject: interchange: tests: counter: emit carries for xc7 Signed-off-by: Alessandro Comodi --- fpga_interchange/examples/tests/counter/counter.v | 8 +++++--- fpga_interchange/examples/tests/counter/run_xilinx.tcl | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'fpga_interchange/examples') diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v index 00f52a20..4b3f343b 100644 --- a/fpga_interchange/examples/tests/counter/counter.v +++ b/fpga_interchange/examples/tests/counter/counter.v @@ -1,13 +1,15 @@ module top(input clk, input rst, output [7:4] io_led); -reg [31:0] counter = 32'b0; +localparam SIZE = 32; -assign io_led = counter >> 22; +reg [SIZE-1:0] counter = SIZE'b0; + +assign io_led = {counter[SIZE-1], counter[25:23]}; always @(posedge clk) begin if(rst) - counter <= 32'b0; + counter <= SIZE'b0; else counter <= counter + 1; end diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl index ffea3b2e..c02cf933 100644 --- a/fpga_interchange/examples/tests/counter/run_xilinx.tcl +++ b/fpga_interchange/examples/tests/counter/run_xilinx.tcl @@ -2,7 +2,7 @@ yosys -import read_verilog $::env(SOURCES) -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp +synth_xilinx -nolutram -nowidelut -nosrl -nodsp techmap -map $::env(TECHMAP) # opt_expr -undriven makes sure all nets are driven, if only by the $undef -- cgit v1.2.3