From 5a7f83c705d6ea52e9e5bb7b182b32040d15a13a Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 16 Feb 2021 12:24:15 -0800 Subject: Add examples invoking FPGA interchange nextpnr. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/examples/wire/Makefile | 8 ++++++++ fpga_interchange/examples/wire/run.tcl | 14 ++++++++++++++ fpga_interchange/examples/wire/wire.v | 5 +++++ fpga_interchange/examples/wire/wire.xdc | 2 ++ 4 files changed, 29 insertions(+) create mode 100644 fpga_interchange/examples/wire/Makefile create mode 100644 fpga_interchange/examples/wire/run.tcl create mode 100644 fpga_interchange/examples/wire/wire.v create mode 100644 fpga_interchange/examples/wire/wire.xdc (limited to 'fpga_interchange/examples/wire') diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile new file mode 100644 index 00000000..49194f53 --- /dev/null +++ b/fpga_interchange/examples/wire/Makefile @@ -0,0 +1,8 @@ +DESIGN := wire +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/wire.json: wire.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/wire/run.tcl b/fpga_interchange/examples/wire/run.tcl new file mode 100644 index 00000000..9127be20 --- /dev/null +++ b/fpga_interchange/examples/wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog wire.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/wire.json diff --git a/fpga_interchange/examples/wire/wire.v b/fpga_interchange/examples/wire/wire.v new file mode 100644 index 00000000..429d05ff --- /dev/null +++ b/fpga_interchange/examples/wire/wire.v @@ -0,0 +1,5 @@ +module top(input i, output o); + +assign o = i; + +endmodule diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc new file mode 100644 index 00000000..e1fce5f0 --- /dev/null +++ b/fpga_interchange/examples/wire/wire.xdc @@ -0,0 +1,2 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] -- cgit v1.2.3