From 9916525418af082a8b83a01b8456ddd3ade129f9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 5 Nov 2020 11:53:55 +0000 Subject: ecp5: Fix handling of CLK/LSR wire attached settings Signed-off-by: David Shah --- ecp5/bitstream.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'ecp5') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index dd954e86..0d168158 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -808,7 +808,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE")); cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR")); - } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id( + } + if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id( fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) { cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE")); @@ -821,7 +822,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex if (ctx->getBoundWireNet(ctx->getWireByName( ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK0")))) == clknet) { cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK")); - } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id( + } + if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id( fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK1")))) == clknet) { cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK")); } -- cgit v1.2.3