From 7c81d4e6307cc226604b14d69ca3fc3eeb47133d Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 20 Jan 2020 20:30:14 +0000 Subject: ecp5: Add SPICB0 IO support Signed-off-by: David Shah --- ecp5/bitstream.cc | 4 ++-- ecp5/trellis_import.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'ecp5') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 207ba048..bc8a6c55 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -178,7 +178,7 @@ static std::string get_pio_tile(Context *ctx, BelId bel) { static const std::set pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"}; static const std::set pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"}; - static const std::set pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"}; static const std::set piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); @@ -215,7 +215,7 @@ static std::string get_pic_tile(Context *ctx, BelId bel) static const std::set picab_r = {"PICR0", "PICR0_DQS2"}; static const std::set piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"}; - static const std::set pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"}; static const std::set picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index c8589b6c..a21c4b3d 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -521,7 +521,7 @@ def write_database(dev_name, chip, ddrg, endianness): loc, bel_idx, bank, func, dqs = pin write_loc(loc, "abs_loc") bba.u32(bel_idx, "bel_index") - if func is not None: + if func is not None and func != "WRITEN": bba.s(func, "function_name") else: bba.r(None, "function_name") -- cgit v1.2.3