From 981522b10ead3b3c2cbc5f9f270b9fae9320395b Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 8 Jul 2018 14:24:32 +0200 Subject: ecp5: Blinky example places and routes Signed-off-by: David Shah --- ecp5/synth/wire.v | 11 +++++++++++ ecp5/synth/wire.ys | 9 +++++++++ 2 files changed, 20 insertions(+) create mode 100644 ecp5/synth/wire.v create mode 100644 ecp5/synth/wire.ys (limited to 'ecp5/synth') diff --git a/ecp5/synth/wire.v b/ecp5/synth/wire.v new file mode 100644 index 00000000..2af68ed2 --- /dev/null +++ b/ecp5/synth/wire.v @@ -0,0 +1,11 @@ +module top(input a_pin, output [3:0] led_pin); + + wire a; + wire [3:0] led; + + TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a)); + TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led)); + + //assign led[0] = !a; + always @(posedge a) led[0] <= !led[0]; +endmodule diff --git a/ecp5/synth/wire.ys b/ecp5/synth/wire.ys new file mode 100644 index 00000000..f916588b --- /dev/null +++ b/ecp5/synth/wire.ys @@ -0,0 +1,9 @@ +read_verilog wire.v +read_verilog -lib cells.v +synth -top top +abc -lut 4 +techmap -map simple_map.v +splitnets +opt_clean +stat +write_json wire.json -- cgit v1.2.3