From 18813f2056e0608ff5dde5737da4d1b0efadca64 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 15 Nov 2018 16:34:22 +0000 Subject: ecp5: Adding real timing data to database Signed-off-by: David Shah --- ecp5/arch.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 56 insertions(+), 5 deletions(-) (limited to 'ecp5/arch.h') diff --git a/ecp5/arch.h b/ecp5/arch.h index aa3c5348..9fb33c9b 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -71,7 +71,7 @@ NPNR_PACKED_STRUCT(struct BelPortPOD { NPNR_PACKED_STRUCT(struct PipInfoPOD { LocationPOD rel_src_loc, rel_dst_loc; int32_t src_idx, dst_idx; - int32_t delay; + int32_t timing_class; int16_t tile_type; int8_t pip_type; int8_t padding_0; @@ -151,6 +151,46 @@ NPNR_PACKED_STRUCT(struct GlobalInfoPOD { int16_t spine_col; }); +NPNR_PACKED_STRUCT(struct CellPropDelayPOD { + int32_t from_port; + int32_t to_port; + int32_t min_delay; + int32_t max_delay; +}); + + +NPNR_PACKED_STRUCT(struct CellSetupHoldPOD { + int32_t sig_port; + int32_t clock_port; + int32_t min_setup; + int32_t max_setup; + int32_t min_hold; + int32_t max_hold; +}); + + +NPNR_PACKED_STRUCT(struct CellTimingPOD { + int32_t cell_type; + int32_t num_prop_delays; + int32_t num_setup_holds; + RelPtr prop_delays; + RelPtr setup_holds; +}); + +NPNR_PACKED_STRUCT(struct PipDelayPOD { + int32_t min_base_delay; + int32_t max_base_delay; + int32_t min_fanout_adder; + int32_t max_fanout_adder; +}); + +NPNR_PACKED_STRUCT(struct SpeedGradePOD { + int32_t num_cell_timings; + int32_t num_pip_classes; + RelPtr cell_timings; + RelPtr pip_classes; +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t width, height; int32_t num_tiles; @@ -163,6 +203,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr package_info; RelPtr pio_info; RelPtr tile_info; + RelPtr speed_grades; }); #if defined(_MSC_VER) @@ -400,13 +441,20 @@ struct ArchArgs LFE5UM5G_85F, } type = NONE; std::string package; - int speed = 6; + enum SpeedGrade + { + SPEED_6, + SPEED_7, + SPEED_8, + SPEED_8_5G, + } speedGrade = SPEED_6; }; struct Arch : BaseCtx { const ChipInfoPOD *chip_info; const PackageInfoPOD *package_info; + const SpeedGradePOD *speed_grade; mutable std::unordered_map bel_by_name; mutable std::unordered_map wire_by_name; @@ -633,7 +681,8 @@ struct Arch : BaseCtx DelayInfo getWireDelay(WireId wire) const { DelayInfo delay; - delay.delay = 0; + delay.min_delay = 0; + delay.max_delay = 0; return delay; } @@ -772,7 +821,8 @@ struct Arch : BaseCtx { DelayInfo delay; NPNR_ASSERT(pip != PipId()); - delay.delay = locInfo(pip)->pip_data[pip.index].delay; + delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay; + delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay; return delay; } @@ -862,7 +912,8 @@ struct Arch : BaseCtx DelayInfo getDelayFromNS(float ns) const { DelayInfo del; - del.delay = delay_t(ns * 1000); + del.min_delay = delay_t(ns * 1000); + del.max_delay = delay_t(ns * 1000); return del; } uint32_t getDelayChecksum(delay_t v) const { return v; } -- cgit v1.2.3 From 3ecd44074833de7f4785cd5fbd77c0570c818e8a Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 15 Nov 2018 17:24:16 +0000 Subject: ecp5: Use new timing data Signed-off-by: David Shah --- ecp5/arch.h | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'ecp5/arch.h') diff --git a/ecp5/arch.h b/ecp5/arch.h index 9fb33c9b..938ca354 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -158,23 +158,21 @@ NPNR_PACKED_STRUCT(struct CellPropDelayPOD { int32_t max_delay; }); - NPNR_PACKED_STRUCT(struct CellSetupHoldPOD { - int32_t sig_port; - int32_t clock_port; - int32_t min_setup; - int32_t max_setup; - int32_t min_hold; - int32_t max_hold; + int32_t sig_port; + int32_t clock_port; + int32_t min_setup; + int32_t max_setup; + int32_t min_hold; + int32_t max_hold; }); - NPNR_PACKED_STRUCT(struct CellTimingPOD { - int32_t cell_type; - int32_t num_prop_delays; - int32_t num_setup_holds; - RelPtr prop_delays; - RelPtr setup_holds; + int32_t cell_type; + int32_t num_prop_delays; + int32_t num_setup_holds; + RelPtr prop_delays; + RelPtr setup_holds; }); NPNR_PACKED_STRUCT(struct PipDelayPOD { @@ -443,11 +441,11 @@ struct ArchArgs std::string package; enum SpeedGrade { - SPEED_6, + SPEED_6 = 0, SPEED_7, SPEED_8, SPEED_8_5G, - } speedGrade = SPEED_6; + } speed = SPEED_6; }; struct Arch : BaseCtx @@ -946,6 +944,10 @@ struct Arch : BaseCtx // Return true if a port is a net bool isGlobalNet(const NetInfo *net) const; + bool getDelayFromTimingDatabase(IdString tctype, IdString from, IdString to, DelayInfo &delay) const; + void getSetupHoldFromTimingDatabase(IdString tctype, IdString clock, IdString port, DelayInfo &setup, + DelayInfo &hold) const; + // ------------------------------------------------- // Placement validity checks bool isValidBelForCell(CellInfo *cell, BelId bel) const; -- cgit v1.2.3 From 2024346f4dc202da9863c1a76d06fe74e9e03055 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 15 Nov 2018 19:10:31 +0000 Subject: ecp5: Consider fanout when calculating pip delays Signed-off-by: David Shah --- ecp5/arch.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'ecp5/arch.h') diff --git a/ecp5/arch.h b/ecp5/arch.h index 938ca354..52cca416 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -461,6 +461,7 @@ struct Arch : BaseCtx std::vector bel_to_cell; std::unordered_map wire_to_net; std::unordered_map pip_to_net; + std::unordered_map wire_fanout; ArchArgs args; Arch(ArchArgs args); @@ -643,6 +644,7 @@ struct Arch : BaseCtx auto pip = it->second.pip; if (pip != PipId()) { + wire_fanout[getPipSrcWire(pip)]--; pip_to_net[pip] = nullptr; } @@ -733,6 +735,7 @@ struct Arch : BaseCtx NPNR_ASSERT(pip_to_net[pip] == nullptr); pip_to_net[pip] = net; + wire_fanout[getPipSrcWire(pip)]++; WireId dst; dst.index = locInfo(pip)->pip_data[pip.index].dst_idx; @@ -747,6 +750,7 @@ struct Arch : BaseCtx { NPNR_ASSERT(pip != PipId()); NPNR_ASSERT(pip_to_net[pip] != nullptr); + wire_fanout[getPipSrcWire(pip)]--; WireId dst; dst.index = locInfo(pip)->pip_data[pip.index].dst_idx; @@ -819,8 +823,14 @@ struct Arch : BaseCtx { DelayInfo delay; NPNR_ASSERT(pip != PipId()); - delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay; - delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay; + int fanout = 0; + auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip)); + if (fnd_fanout != wire_fanout.end()) + fanout = fnd_fanout->second; + delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay + + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder; + delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay + + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder; return delay; } -- cgit v1.2.3 From 13244e513b2a7454f2fa6d952df334439d28588a Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 16 Nov 2018 12:59:27 +0000 Subject: ecp5: Fix db import, improve timing data debugging Signed-off-by: David Shah --- ecp5/arch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'ecp5/arch.h') diff --git a/ecp5/arch.h b/ecp5/arch.h index 52cca416..cf30876b 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -827,6 +827,7 @@ struct Arch : BaseCtx auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip)); if (fnd_fanout != wire_fanout.end()) fanout = fnd_fanout->second; + NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes); delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder; delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay -- cgit v1.2.3 From 1ae722272a1d6751065e47bbd0d4fcc29a6a97fe Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 16 Nov 2018 13:27:03 +0000 Subject: ecp5: clangformat timing changes Signed-off-by: David Shah --- ecp5/arch.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'ecp5/arch.h') diff --git a/ecp5/arch.h b/ecp5/arch.h index cf30876b..a68673f4 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -828,10 +828,12 @@ struct Arch : BaseCtx if (fnd_fanout != wire_fanout.end()) fanout = fnd_fanout->second; NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes); - delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay - + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder; - delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay - + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder; + delay.min_delay = + speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay + + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder; + delay.max_delay = + speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay + + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder; return delay; } -- cgit v1.2.3