From a65f0e57b9affbcb2a5387347457d78d995b7d35 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Fri, 2 Jul 2021 14:00:20 +1000 Subject: Add IO_PORT parsing Signed-off-by: YRabbit --- gowin/arch.cc | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index e8a14522..63277438 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -483,37 +483,50 @@ DelayQuad Arch::getWireTypeDelay(IdString wire) void Arch::read_cst(std::istream &in) { - std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+);"); + std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+) *;.*"); + std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^ =;]+)=([^ =;]+) *;.*"); std::smatch match; std::string line; + boolean io_loc; while (!in.eof()) { std::getline(in, line); + io_loc = true; if (!std::regex_match(line, match, iobre)) { // empty line or comment - if (line.empty() || line.rfind("//", 0) == 0) { + if (line.empty()) == 0) { continue; } else { - log_warning("Invalid constraint: %s\n", line.c_str()); - continue; + if (!std::regex_match(line, match, portre)) { + io_loc = false; + } else if (line.rfind("//", 0) == 0) { + log_warning("Invalid constraint: %s\n", line.c_str()); + continue; + } } } // std::cout << match[1] << " " << match[2] << std::endl; + IdString net = id(match[1]); - IdString pinname = id(match[2]); - const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index); - if (belname == nullptr) - log_error("Pin %s not found\n", pinname.c_str(this)); - // BelId bel = getBelByName(belname->src_id); - // for (auto cell : sorted(cells)) { - // std::cout << cell.first.str(this) << std::endl; - // } auto it = cells.find(net); if (it == cells.end()) { log_info("Cell %s not found\n", net.c_str(this)); continue; } - std::string bel = IdString(belname->src_id).str(this); - it->second->attrs[IdString(ID_BEL)] = bel; + if (io_loc) { // IO_LOC name pin + IdString pinname = id(match[2]); + const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index); + if (belname == nullptr) + log_error("Pin %s not found\n", pinname.c_str(this)); + // BelId bel = getBelByName(belname->src_id); + // for (auto cell : sorted(cells)) { + // std::cout << cell.first.str(this) << std::endl; + // } + std::string bel = IdString(belname->src_id).str(this); + it->second->attrs[IdString(ID_BEL)] = bel; + } else { // IO_PORT attr=value + // XXX + log_info("XXX port attr found %s=%s\n", match[2], match[3]); + } } } -- cgit v1.2.3 From 9443267717cf0ea2278f800127db7fd9e962650f Mon Sep 17 00:00:00 2001 From: YRabbit Date: Fri, 2 Jul 2021 14:58:17 +1000 Subject: Syntax Signed-off-by: YRabbit --- gowin/arch.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index 63277438..8dc5657c 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -487,13 +487,13 @@ void Arch::read_cst(std::istream &in) std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^ =;]+)=([^ =;]+) *;.*"); std::smatch match; std::string line; - boolean io_loc; + bool io_loc; while (!in.eof()) { std::getline(in, line); io_loc = true; if (!std::regex_match(line, match, iobre)) { // empty line or comment - if (line.empty()) == 0) { + if (line.empty() == 0) { continue; } else { if (!std::regex_match(line, match, portre)) { @@ -525,7 +525,7 @@ void Arch::read_cst(std::istream &in) it->second->attrs[IdString(ID_BEL)] = bel; } else { // IO_PORT attr=value // XXX - log_info("XXX port attr found %s=%s\n", match[2], match[3]); + log_info("XXX port attr found %s=%s\n", match.str(2).c_str(), match.str(3).c_str()); } } } -- cgit v1.2.3 From 5c5982c50a63c83dba2f68e9d5dcc2bb67cc4c67 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 3 Jul 2021 08:23:25 +1000 Subject: Fix parser. Comments and IO_PORT Signed-off-by: YRabbit --- gowin/arch.cc | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index 8dc5657c..b4c8c96f 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -492,19 +492,17 @@ void Arch::read_cst(std::istream &in) std::getline(in, line); io_loc = true; if (!std::regex_match(line, match, iobre)) { - // empty line or comment - if (line.empty() == 0) { - continue; - } else { - if (!std::regex_match(line, match, portre)) { - io_loc = false; - } else if (line.rfind("//", 0) == 0) { + if (std::regex_match(line, match, portre)) { + io_loc = false; + } else { + if ( (!line.empty()) && (line.rfind("//", 0) == std::string::npos)) { log_warning("Invalid constraint: %s\n", line.c_str()); - continue; } - } - } - // std::cout << match[1] << " " << match[2] << std::endl; + continue; + } + } + + //std::cout << match[1] << " " << match[2] << std::endl; IdString net = id(match[1]); auto it = cells.find(net); -- cgit v1.2.3 From baa68fa4c13b2c383f976eb22d6bfddbcb598d62 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Mon, 5 Jul 2021 08:31:01 +1000 Subject: Parser Signed-off-by: YRabbit --- gowin/arch.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gowin/arch.cc b/gowin/arch.cc index b4c8c96f..db8bddaf 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -18,6 +18,7 @@ * */ +#include #include #include #include @@ -524,6 +525,14 @@ void Arch::read_cst(std::istream &in) } else { // IO_PORT attr=value // XXX log_info("XXX port attr found %s=%s\n", match.str(2).c_str(), match.str(3).c_str()); + std::string attr = match[2]; + std::string value = match[3]; + boost::algorithm::to_upper(attr); + boost::algorithm::to_upper(value); + it->second->attrs[id(attr)] = value; + //for (auto at : it->second->attrs) { + // std::cout << at.first.str(this) << "=" << at.second.as_string() << std::endl; + //} } } } -- cgit v1.2.3 From fd7734f0006d6522dea1ea4ea29750c8bafc77c4 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 7 Jul 2021 08:36:05 +1000 Subject: Wip parser Signed-off-by: YRabbit --- gowin/arch.cc | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index db8bddaf..7fda387a 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -485,7 +485,7 @@ DelayQuad Arch::getWireTypeDelay(IdString wire) void Arch::read_cst(std::istream &in) { std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+) *;.*"); - std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^ =;]+)=([^ =;]+) *;.*"); + std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^ =;]+=[^ =;]+) *;.*"); std::smatch match; std::string line; bool io_loc; @@ -503,8 +503,6 @@ void Arch::read_cst(std::istream &in) } } - //std::cout << match[1] << " " << match[2] << std::endl; - IdString net = id(match[1]); auto it = cells.find(net); if (it == cells.end()) { @@ -516,23 +514,13 @@ void Arch::read_cst(std::istream &in) const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index); if (belname == nullptr) log_error("Pin %s not found\n", pinname.c_str(this)); - // BelId bel = getBelByName(belname->src_id); - // for (auto cell : sorted(cells)) { - // std::cout << cell.first.str(this) << std::endl; - // } std::string bel = IdString(belname->src_id).str(this); it->second->attrs[IdString(ID_BEL)] = bel; } else { // IO_PORT attr=value - // XXX - log_info("XXX port attr found %s=%s\n", match.str(2).c_str(), match.str(3).c_str()); - std::string attr = match[2]; - std::string value = match[3]; + std::string attr = "&"; + attr += match[2]; boost::algorithm::to_upper(attr); - boost::algorithm::to_upper(value); - it->second->attrs[id(attr)] = value; - //for (auto at : it->second->attrs) { - // std::cout << at.first.str(this) << "=" << at.second.as_string() << std::endl; - //} + it->second->attrs[id(attr)] = 0; } } } -- cgit v1.2.3 From 5d8b27710d333ff969556edeb55ba3ab6bbfa619 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 7 Jul 2021 22:02:43 +1000 Subject: Fix boolean value. Signed-off-by: YRabbit --- gowin/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index 7fda387a..f47d00f7 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -520,7 +520,7 @@ void Arch::read_cst(std::istream &in) std::string attr = "&"; attr += match[2]; boost::algorithm::to_upper(attr); - it->second->attrs[id(attr)] = 0; + it->second->attrs[id(attr)] = 1; } } } -- cgit v1.2.3 From d613626ab998fd24d467101253fcd4e563669078 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 7 Jul 2021 22:53:49 +1000 Subject: Fix formating Signed-off-by: YRabbit --- gowin/arch.cc | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index f47d00f7..438c6ca9 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -488,20 +488,20 @@ void Arch::read_cst(std::istream &in) std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^ =;]+=[^ =;]+) *;.*"); std::smatch match; std::string line; - bool io_loc; + bool io_loc; while (!in.eof()) { std::getline(in, line); - io_loc = true; + io_loc = true; if (!std::regex_match(line, match, iobre)) { - if (std::regex_match(line, match, portre)) { - io_loc = false; - } else { - if ( (!line.empty()) && (line.rfind("//", 0) == std::string::npos)) { - log_warning("Invalid constraint: %s\n", line.c_str()); - } - continue; - } - } + if (std::regex_match(line, match, portre)) { + io_loc = false; + } else { + if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) { + log_warning("Invalid constraint: %s\n", line.c_str()); + } + continue; + } + } IdString net = id(match[1]); auto it = cells.find(net); @@ -509,19 +509,19 @@ void Arch::read_cst(std::istream &in) log_info("Cell %s not found\n", net.c_str(this)); continue; } - if (io_loc) { // IO_LOC name pin - IdString pinname = id(match[2]); - const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index); - if (belname == nullptr) - log_error("Pin %s not found\n", pinname.c_str(this)); - std::string bel = IdString(belname->src_id).str(this); - it->second->attrs[IdString(ID_BEL)] = bel; - } else { // IO_PORT attr=value - std::string attr = "&"; - attr += match[2]; - boost::algorithm::to_upper(attr); - it->second->attrs[id(attr)] = 1; - } + if (io_loc) { // IO_LOC name pin + IdString pinname = id(match[2]); + const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index); + if (belname == nullptr) + log_error("Pin %s not found\n", pinname.c_str(this)); + std::string bel = IdString(belname->src_id).str(this); + it->second->attrs[IdString(ID_BEL)] = bel; + } else { // IO_PORT attr=value + std::string attr = "&"; + attr += match[2]; + boost::algorithm::to_upper(attr); + it->second->attrs[id(attr)] = 0; + } } } -- cgit v1.2.3 From 881fd97c5aaa8c8898bd6ffa7d221bca5317a456 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Thu, 8 Jul 2021 07:09:30 +1000 Subject: Fix the boolean. Signed-off-by: YRabbit --- gowin/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gowin/arch.cc b/gowin/arch.cc index 438c6ca9..e4dce329 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -520,7 +520,7 @@ void Arch::read_cst(std::istream &in) std::string attr = "&"; attr += match[2]; boost::algorithm::to_upper(attr); - it->second->attrs[id(attr)] = 0; + it->second->attrs[id(attr)] = 1; } } } -- cgit v1.2.3 From dc0819b01a6bb976ea29151da2cd95e8227f8e08 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 7 Jul 2021 19:16:48 +0200 Subject: interchange: reduce run-time to check dedicated interconnect Signed-off-by: Alessandro Comodi --- fpga_interchange/arch.h | 2 +- fpga_interchange/arch_pack_clusters.cc | 7 ++-- fpga_interchange/chipdb.h | 1 + fpga_interchange/dedicated_interconnect.cc | 62 +++++++++++++++++++++++++++++- 4 files changed, 67 insertions(+), 5 deletions(-) diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 896a603a..630c4480 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -855,7 +855,7 @@ struct Arch : ArchAPI const CellInfo *cell = tile_status.boundcells[bel.index]; if (cell != nullptr) { - if (cell->cluster == ClusterId() && !dedicated_interconnect.isBelLocationValid(bel, cell)) + if (!dedicated_interconnect.isBelLocationValid(bel, cell)) return false; if (io_port_types.count(cell->type)) { diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc index 18162aa4..f4e50233 100644 --- a/fpga_interchange/arch_pack_clusters.cc +++ b/fpga_interchange/arch_pack_clusters.cc @@ -193,6 +193,8 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel, const Context *ctx = getCtx(); const Cluster &packed_cluster = clusters.at(cluster); + auto &cluster_data = cluster_info(chip_info, packed_cluster.index); + CellInfo *root_cell = getClusterRootCell(cluster); if (!ctx->isValidBelForCellType(root_cell->type, root_bel)) return false; @@ -205,8 +207,6 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel, next_bel = root_bel; } else { // Find next chained cluster node - auto &cluster_data = cluster_info(chip_info, packed_cluster.index); - IdString next_bel_pin(cluster_data.chainable_ports[0].bel_source); WireId next_bel_pin_wire = ctx->getBelPinWire(next_bel, next_bel_pin); next_bel = BelId(); @@ -256,7 +256,8 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel, WireId bel_pin_wire = ctx->getBelPinWire(next_bel, bel_pin); ExpansionDirection direction = port_type == PORT_IN ? CLUSTER_UPHILL_DIR : CLUSTER_DOWNHILL_DIR; - pool cluster_bels = find_cluster_bels(ctx, bel_pin_wire, direction); + pool cluster_bels = + find_cluster_bels(ctx, bel_pin_wire, direction, (bool)cluster_data.out_of_site_clusters); if (cluster_bels.size() == 0) continue; diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index fde35e7f..6879f02a 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -421,6 +421,7 @@ NPNR_PACKED_STRUCT(struct ClusterPOD { RelSlice root_cell_types; RelSlice chainable_ports; RelSlice cluster_cells_map; + uint32_t out_of_site_clusters; }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc index 1254b367..7658d579 100644 --- a/fpga_interchange/dedicated_interconnect.cc +++ b/fpga_interchange/dedicated_interconnect.cc @@ -39,6 +39,12 @@ enum WireNodeState IN_SOURCE_SITE = 2 }; +enum ExpansionDirection +{ + EXPAND_DOWNHILL = 0, + EXPAND_UPHILL = 1 +}; + struct WireNode { WireId wire; @@ -52,6 +58,50 @@ struct WireNode // interconnect. constexpr int kMaxDepth = 6; +static uint32_t get_num_pips(const Context *ctx, WireId wire, ExpansionDirection direction) +{ + uint32_t num_pips = 0; + + if (direction == EXPAND_DOWNHILL) { + for (PipId pip : ctx->getPipsDownhill(wire)) { + auto &pip_data = pip_info(ctx->chip_info, pip); + if (pip_data.pseudo_cell_wires.size() > 0) + continue; + + if (ctx->getPipDstWire(pip) == WireId()) + continue; + + if (ctx->is_pip_synthetic(pip)) + continue; + + if (ctx->is_site_port(pip)) + continue; + + num_pips++; + } + } else { + NPNR_ASSERT(direction == EXPAND_UPHILL); + for (PipId pip : ctx->getPipsUphill(wire)) { + auto &pip_data = pip_info(ctx->chip_info, pip); + if (pip_data.pseudo_cell_wires.size() > 0) + continue; + + if (ctx->getPipSrcWire(pip) == WireId()) + continue; + + if (ctx->is_pip_synthetic(pip)) + continue; + + if (ctx->is_site_port(pip)) + continue; + + num_pips++; + } + } + + return num_pips; +} + void DedicatedInterconnect::init(const Context *ctx) { this->ctx = ctx; @@ -99,6 +149,16 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B WireNode node_to_expand = nodes_to_expand.back(); nodes_to_expand.pop_back(); + auto num_pips = get_num_pips(ctx, node_to_expand.wire, EXPAND_DOWNHILL); + + // Usually, dedicated interconnects do not have more than one PIPs in the out-of-site + if (node_to_expand.depth > 1 && node_to_expand.state == IN_ROUTING && num_pips > 1) { + if (ctx->verbose) + log_info("Wire %s is on a non-dedicated path (number of pips %d)\n", + ctx->nameOfWire(node_to_expand.wire), num_pips); + continue; + } + for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) { if (ctx->is_pip_synthetic(pip)) { continue; @@ -147,7 +207,7 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B #ifdef DEBUG_EXPANSION log_info(" - Not dedicated site routing because loop!"); #endif - return false; + continue; } next_node.state = IN_SINK_SITE; break; -- cgit v1.2.3 From fbd291deaf46201e0d69938a7768ea271ff084ee Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Thu, 8 Jul 2021 16:43:30 +0200 Subject: interchange: update chipdb version Signed-off-by: Alessandro Comodi --- fpga_interchange/chipdb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 6879f02a..15ef8b07 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 11; +static constexpr int32_t kExpectedChipInfoVersion = 12; // Flattened site indexing. // -- cgit v1.2.3 From b64642fc9919a009fc4c286a15fc255dff549ed5 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Thu, 8 Jul 2021 16:41:17 +0200 Subject: interchange: bump python-interchange version Signed-off-by: Alessandro Comodi --- .github/workflows/interchange_ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml index d7dca9da..9b2ba027 100644 --- a/.github/workflows/interchange_ci.yml +++ b/.github/workflows/interchange_ci.yml @@ -114,7 +114,7 @@ jobs: env: RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange - PYTHON_INTERCHANGE_TAG: v0.0.15 + PYTHON_INTERCHANGE_TAG: v0.0.16 PRJOXIDE_REVISION: 1bf30dee9c023c4c66cfc44fd0bc28addd229c89 DEVICE: ${{ matrix.device }} run: | -- cgit v1.2.3