From 6c38df7295747ddd37a751ea5de2a73e95a021d1 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Jul 2018 13:22:46 +0200 Subject: ice40: Adding cell definition for DSPs Signed-off-by: David Shah --- common/nextpnr.h | 3 +-- ice40/arch.cc | 8 +++---- ice40/archdefs.h | 2 +- ice40/cells.cc | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ice40/cells.h | 2 ++ 5 files changed, 80 insertions(+), 7 deletions(-) diff --git a/common/nextpnr.h b/common/nextpnr.h index 7aadfae4..bc64adb5 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -84,9 +84,8 @@ inline bool assert_fail_impl_str(std::string message, const char *expr_str, cons throw assertion_failure(message, expr_str, filename, line); } - #define NPNR_ASSERT(cond) ((void)((cond) || (assert_fail_impl(#cond, #cond, __FILE__, __LINE__)))) -#define NPNR_ASSERT_MSG(cond, msg) ((void)((cond) || (assert_fail_impl(msg, #cond, __FILE__, __LINE__)))) +#define NPNR_ASSERT_MSG(cond, msg) ((void)((cond) || (assert_fail_impl(msg, #cond, __FILE__, __LINE__)))) #define NPNR_ASSERT_FALSE(msg) (assert_fail_impl(msg, "false", __FILE__, __LINE__)) #define NPNR_ASSERT_FALSE_STR(msg) (assert_fail_impl_str(msg, "false", __FILE__, __LINE__)) diff --git a/ice40/arch.cc b/ice40/arch.cc index 0decc513..1aa02294 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -44,8 +44,8 @@ IdString Arch::belTypeToId(BelType type) const return id("ICESTORM_PLL"); if (type == TYPE_SB_WARMBOOT) return id("SB_WARMBOOT"); - if (type == TYPE_SB_MAC16) - return id("SB_MAC16"); + if (type == TYPE_ICESTORM_DSP) + return id("ICESTORM_DSP"); if (type == TYPE_ICESTORM_HFOSC) return id("ICESTORM_HFOSC"); if (type == TYPE_ICESTORM_LFOSC) @@ -79,8 +79,8 @@ BelType Arch::belTypeFromId(IdString type) const return TYPE_ICESTORM_PLL; if (type == id("SB_WARMBOOT")) return TYPE_SB_WARMBOOT; - if (type == id("SB_MAC16")) - return TYPE_SB_MAC16; + if (type == id("ICESTORM_DSP")) + return TYPE_ICESTORM_DSP; if (type == id("ICESTORM_HFOSC")) return TYPE_ICESTORM_HFOSC; if (type == id("ICESTORM_LFOSC")) diff --git a/ice40/archdefs.h b/ice40/archdefs.h index cf8a78f4..55e2c2fb 100644 --- a/ice40/archdefs.h +++ b/ice40/archdefs.h @@ -54,7 +54,7 @@ enum BelType : int32_t TYPE_SB_GB, TYPE_ICESTORM_PLL, TYPE_SB_WARMBOOT, - TYPE_SB_MAC16, + TYPE_ICESTORM_DSP, TYPE_ICESTORM_HFOSC, TYPE_ICESTORM_LFOSC, TYPE_SB_I2C, diff --git a/ice40/cells.cc b/ice40/cells.cc index 8e8679ee..f07e0d22 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -142,6 +142,71 @@ std::unique_ptr create_ice_cell(Context *ctx, IdString type, std::stri for (int i = 0; i < 4; i++) { add_port(ctx, new_cell.get(), "MASKWREN_" + std::to_string(i), PORT_IN); } + } else if (type == ctx->id("ICESTORM_DSP")) { + new_cell->params[ctx->id("NEG_TRIGGER")] = "0"; + + new_cell->params[ctx->id("C_REG")] = "0"; + new_cell->params[ctx->id("A_REG")] = "0"; + new_cell->params[ctx->id("B_REG")] = "0"; + new_cell->params[ctx->id("D_REG")] = "0"; + new_cell->params[ctx->id("TOP_8x8_MULT_REG")] = "0"; + new_cell->params[ctx->id("BOT_8x8_MULT_REG")] = "0"; + new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG1")] = "0"; + new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG2")] = "0"; + + new_cell->params[ctx->id("TOPOUTPUT_SELECT")] = "0"; + new_cell->params[ctx->id("TOPADDSUB_LOWERINPUT")] = "0"; + new_cell->params[ctx->id("TOPADDSUB_UPPERINPUT")] = "0"; + new_cell->params[ctx->id("TOPADDSUB_CARRYSELECT")] = "0"; + + new_cell->params[ctx->id("BOTOUTPUT_SELECT")] = "0"; + new_cell->params[ctx->id("BOTADDSUB_LOWERINPUT")] = "0"; + new_cell->params[ctx->id("BOTADDSUB_UPPERINPUT")] = "0"; + new_cell->params[ctx->id("BOTADDSUB_CARRYSELECT")] = "0"; + + new_cell->params[ctx->id("MODE_8x8")] = "0"; + new_cell->params[ctx->id("A_SIGNED")] = "0"; + new_cell->params[ctx->id("B_SIGNED")] = "0"; + + add_port(ctx, new_cell.get(), "CLK", PORT_IN); + add_port(ctx, new_cell.get(), "CE", PORT_IN); + for (int i = 0; i < 16; i++) { + add_port(ctx, new_cell.get(), "C_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "A_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "B_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "D_" + std::to_string(i), PORT_IN); + } + add_port(ctx, new_cell.get(), "AHOLD", PORT_IN); + add_port(ctx, new_cell.get(), "BHOLD", PORT_IN); + add_port(ctx, new_cell.get(), "CHOLD", PORT_IN); + add_port(ctx, new_cell.get(), "DHOLD", PORT_IN); + + add_port(ctx, new_cell.get(), "IRSTTOP", PORT_IN); + add_port(ctx, new_cell.get(), "IRSTBOT", PORT_IN); + add_port(ctx, new_cell.get(), "ORSTTOP", PORT_IN); + add_port(ctx, new_cell.get(), "ORSTBOT", PORT_IN); + + add_port(ctx, new_cell.get(), "OLOADTOP", PORT_IN); + add_port(ctx, new_cell.get(), "OLOADBOT", PORT_IN); + + add_port(ctx, new_cell.get(), "ADDSUBTOP", PORT_IN); + add_port(ctx, new_cell.get(), "ADDSUBBOT", PORT_IN); + + add_port(ctx, new_cell.get(), "OHOLDTOP", PORT_IN); + add_port(ctx, new_cell.get(), "OHOLDBOT", PORT_IN); + + add_port(ctx, new_cell.get(), "CI", PORT_IN); + add_port(ctx, new_cell.get(), "ACCUMCI", PORT_IN); + add_port(ctx, new_cell.get(), "SIGNEXTIN", PORT_IN); + + for (int i = 0; i < 32; i++) { + add_port(ctx, new_cell.get(), "O_" + std::to_string(i), PORT_OUT); + } + + add_port(ctx, new_cell.get(), "CO", PORT_OUT); + add_port(ctx, new_cell.get(), "ACCUMCO", PORT_OUT); + add_port(ctx, new_cell.get(), "SIGNEXTOUT", PORT_OUT); + } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } @@ -258,6 +323,8 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port) if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM")) return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK") || port.port == ctx->id("RCLKN") || port.port == ctx->id("WCLKN"); + if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP")) + return port.port == ctx->id("CLK"); return false; } @@ -269,6 +336,9 @@ bool is_reset_port(const BaseCtx *ctx, const PortRef &port) return port.port == ctx->id("R") || port.port == ctx->id("S"); if (port.cell->type == ctx->id("ICESTORM_LC")) return port.port == ctx->id("SR"); + if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP")) + return port.port == ctx->id("IRSTTOP") || port.port == ctx->id("IRSTBOT") || port.port == ctx->id("ORSTTOP") || + port.port == ctx->id("ORSTBOT"); return false; } @@ -280,6 +350,8 @@ bool is_enable_port(const BaseCtx *ctx, const PortRef &port) return port.port == ctx->id("E"); if (port.cell->type == ctx->id("ICESTORM_LC")) return port.port == ctx->id("CEN"); + if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP")) + return port.port == ctx->id("CE"); return false; } diff --git a/ice40/cells.h b/ice40/cells.h index 9f99835d..2f9c77e8 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -69,6 +69,8 @@ inline bool is_sb_hfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell- inline bool is_sb_spram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_SPRAM256KA"); } +inline bool is_sb_mac16(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_MAC16"); } + // Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports // as needed. Set no_dff if a DFF is not being used, so that the output // can be reconnected -- cgit v1.2.3