From 5dd1e5e51e65d1efdd2f84c10a2b751e3228b982 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 8 Nov 2019 17:15:12 +0100
Subject: return FF_USED, formatting, correct INIT

---
 .gitignore                    |  3 +++
 generic/cells.cc              | 14 ++++++++++++--
 generic/examples/bitstream.py |  1 +
 generic/synth/prims.v         |  7 ++++---
 4 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/.gitignore b/.gitignore
index 9b3ffd02..9796d242 100644
--- a/.gitignore
+++ b/.gitignore
@@ -19,6 +19,9 @@ CMakeCache.txt
 .*.swp
 a.out
 *.json
+*.dot
+*.il
+/generic/examples/blinky.png
 build/
 *.asc
 *.bin
diff --git a/generic/cells.cc b/generic/cells.cc
index 3b754406..2b555f62 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -42,8 +42,9 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
     }
     new_cell->type = type;
     if (type == ctx->id("GENERIC_SLICE")) {
-        new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K);
+        new_cell->params[ctx->id("K")] = ctx->args.K;
         new_cell->params[ctx->id("INIT")] = 0;
+        new_cell->params[ctx->id("FF_USED")] = 0;
 
         for (int i = 0; i < ctx->args.K; i++)
             add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
@@ -80,16 +81,25 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
     }
 
     if (no_dff) {
+        lc->params[ctx->id("FF_USED")] = 0;
         replace_port(lut, ctx->id("Q"), lc, ctx->id("F"));
     }
 }
 
 void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 {
+    lc->params[ctx->id("FF_USED")] = 1;
     replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
 
     if (pass_thru_lut) {
-        lc->params[ctx->id("INIT")] = 0xAAAA;
+        // Fill LUT with alternating 10
+        const int init_size = 1 << lc->params[ctx->id("K")].as_int64();
+        std::string init;
+        init.reserve(init_size);
+        for(int i = 0; i < init_size; i+=2)
+            init.append("10");
+        lc->params[ctx->id("INIT")] = Property::from_string(init);
+
         replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
     }
 
diff --git a/generic/examples/bitstream.py b/generic/examples/bitstream.py
index 6cd63a58..7f0b5c07 100644
--- a/generic/examples/bitstream.py
+++ b/generic/examples/bitstream.py
@@ -6,6 +6,7 @@ from simple_config import K
 param_map = {
 	("GENERIC_SLICE", "K"): ParameterConfig(write=False),
 	("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
+	("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
 
 	("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
 	("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
diff --git a/generic/synth/prims.v b/generic/synth/prims.v
index 47a5df0f..acce585c 100644
--- a/generic/synth/prims.v
+++ b/generic/synth/prims.v
@@ -21,19 +21,20 @@ endmodule
 module GENERIC_SLICE #(
 	parameter K = 4,
 	parameter [2**K-1:0] INIT = 0,
+  parameter FF_USED = 1'b0
 ) (
 	input CLK,
 	input [K-1:0] I,
   output F,
 	output Q
 );
-  wire f_wire;
+	wire f_wire;
 	
 	LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
 
-  DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
+	DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
 
-  assign F = f_wire;
+	assign F = f_wire;
 endmodule
 
 module GENERIC_IOB #(
-- 
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