From 45c33e9dcfb215493e31dc53a068b5dd1860a367 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 23 Feb 2021 06:51:40 -0500 Subject: machxo2: Add a special case for pips whose config bits are in multiple tiles. --- machxo2/bitstream.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index 62d1be75..ed67975a 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -115,9 +115,21 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) static void set_pip(Context *ctx, ChipConfig &cc, PipId pip) { std::string tile = ctx->get_pip_tilename(pip); + std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pips_data[pip.index].tile_type].get(); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); + + // Special case pips whose config bits are spread across tiles. + if (source == "G_PCLKCIBVIQT0" && sink == "G_VPRXCLKI0") { + if (tile_type == "CENTER7") { + cc.tiles[ctx->get_tile_by_type("CENTER8")].add_arc(sink, source); + } else if (tile_type == "CENTER8") { + cc.tiles[ctx->get_tile_by_type("CENTER7")].add_arc(sink, source); + } else { + NPNR_ASSERT_FALSE("Tile does not contain special-cased pip"); + } + } } static std::vector int_to_bitvector(int val, int size) -- cgit v1.2.3