From 35e9ec773776354c7a5bf2d5d2692c78111b603c Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Sun, 18 Nov 2018 19:16:08 +0100 Subject: ice40: Minor fix in predicate checking for logic port - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut --- ice40/pack.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/ice40/pack.cc b/ice40/pack.cc index c91c97be..ece352a7 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -461,8 +461,9 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port) { if (is_clock_port(ctx, port) || is_reset_port(ctx, port) || is_enable_port(ctx, port)) return false; - return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && - port.cell->type != ctx->id("SB_GB"); + return !is_sb_io(ctx, port.cell) && + !is_gbuf(ctx, port.cell) && + !is_sb_pll40(ctx, port.cell); } static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic) -- cgit v1.2.3