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| * | Improve ic40 gfxClifford Wolf2018-07-103-164/+216
| * | Add ice40 LC output gfxClifford Wolf2018-07-092-3/+30
| * | Make logic cell positioning a constantDavid Shah2018-07-093-6/+12
| * | Adding all LUT input wiresDavid Shah2018-07-091-3/+6
| * | Add constants for switchbox locationsDavid Shah2018-07-092-28/+63
| * | Reorder gfx.h, add LUT0 inputsDavid Shah2018-07-092-22/+35
| * | Add ice40 gfx right vertical span-4Clifford Wolf2018-07-092-54/+78
| * | Vertical wires and span-12 wiresClifford Wolf2018-07-092-2/+158
| * | Make LCs smaller and move them downDavid Shah2018-07-091-6/+6
| * | Add switchboxesDavid Shah2018-07-091-3/+41
| * | Add horizontal ice40 span4 wire gfxClifford Wolf2018-07-091-0/+49
| * | Add lutff_global switchboxDavid Shah2018-07-091-0/+8
| * | Add ice40 wire gfx enumsClifford Wolf2018-07-093-1/+489
| * | Reduce line width, adding some switchboxesDavid Shah2018-07-091-4/+28
* | | ecp5: Working on arch implementationDavid Shah2018-07-111-4/+4
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* | Added ICE40_HX1K_ONLY check in gui and mainMiodrag Milanovic2018-07-101-0/+4
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* Python executable filename could be differentMiodrag Milanovic2018-07-081-2/+2
* Added selection of chip and pacakge on new projet in GUIMiodrag Milanovic2018-07-071-1/+1
* typeof to decltypeMiodrag Milanovic2018-07-051-38/+38
* python: Convert empty BelId to NoneDavid Shah2018-07-042-3/+9
* python: Renaming and fixing 'generic' buildDavid Shah2018-07-041-0/+0
* python: Update wrapper for non-unique_ptr mapsDavid Shah2018-07-042-57/+88
* ice40: Near-complete Arch bindngsDavid Shah2018-07-041-5/+47
* python: Adding more wrapped bindings for ice40David Shah2018-07-041-23/+25
* python: Developing context wrappers for mapsDavid Shah2018-07-041-0/+16
* python: Adding more bindingsDavid Shah2018-07-041-4/+27
* python: Add context wrapper support for rangesDavid Shah2018-07-041-23/+20
* Progress on new wrapper systemDavid Shah2018-07-041-30/+42
* python: Restructuring wrapper systemDavid Shah2018-07-041-22/+43
* Add NPNR_ASSERT_FALSE, use in bitstream.ccDavid Shah2018-07-041-2/+2
* refactor: Replace assert with NPNR_ASSERTDavid Shah2018-07-048-131/+100
* Building using MSVC worksMiodrag Milanovic2018-07-046-16/+93
* Add opetion to defie ICEBOX_ROOT, fix compile on other locationMiodrag Milanovic2018-07-032-3/+6
* added parameter to callMiodrag Milanovic2018-07-031-1/+1
* Make chibdb.py able to generate pure binary outputMiodrag Milanovic2018-07-031-5/+27
* ice40: Improving routeability of carriesDavid Shah2018-07-031-6/+1
* ice40: Another carry timing fixDavid Shah2018-07-031-5/+4
* ice40: Fix carry timing pathsDavid Shah2018-07-031-3/+3
* Fixed macros and includes for MSVCMiodrag Milanovic2018-07-033-14/+30
* Improve blinky testbench, double blink frequencyClifford Wolf2018-06-302-4/+7
* Split "arch.h" in "arch.h" and "archdefs.h"Clifford Wolf2018-06-292-142/+138
* ice40: UltraPlus SPRAM workingDavid Shah2018-06-296-9/+66
* Improving the SA+legalisation flowDavid Shah2018-06-292-13/+14
* Tidying up the SA placerDavid Shah2018-06-291-3/+3
* ice40: Fix carry packing in some degenerate casesDavid Shah2018-06-291-23/+18
* Integrating SA placer and legaliserDavid Shah2018-06-291-1/+0
* ice40: Reworking placement legalisation to allow integration with SA placerDavid Shah2018-06-293-41/+116
* clangformat cleanupMiodrag Milanovic2018-06-281-6/+4
* ice40: PLace legaliser produces a design that is at least routable for picosocDavid Shah2018-06-282-1/+19
* Debugging carry legalisationDavid Shah2018-06-281-5/+10
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