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* Remove concept of project and code connectedMiodrag Milanovic2019-06-131-76/+0
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* Use properties for settings and save in jsonMiodrag Milanovic2019-06-121-1/+1
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* Save top level attrs and store current stepMiodrag Milanovic2019-06-072-0/+3
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* Add vcc and gnd nets and cells only if neededMiodrag Milanovic2019-06-071-5/+20
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* CleanupMiodrag Milanovic2019-06-072-13/+0
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* WIP saving/loading attributesMiodrag Milanovic2019-06-073-4/+23
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* Revert "Do not add VCC if not used, loading json works"Miodrag Milanovic2019-06-021-6/+5
| | | | This reverts commit f1b3a14bc23ccee6acaf6bbe27827523dc13c111.
* Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
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* Do not add VCC if not used, loading json worksMiodrag Milanovic2019-05-311-5/+6
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* ice40: Add support for HFOSC trimmingSylvain Munaut2019-05-131-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #270 from smunaut/sb_io_conflictDavid Shah2019-04-172-2/+38
|\ | | | | SB IO conflict checks
| * ice40: Check for SB_IO shared wires conflicts in isValidBelForCellSylvain Munaut2019-04-171-0/+36
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrsSylvain Munaut2019-04-171-2/+2
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Only create padin gbuf for PLLs if global output actually usedSylvain Munaut2019-04-171-11/+38
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Take placed SB_GBs into account when placing PLLsSylvain Munaut2019-04-161-9/+55
|/ | | | | | | | | | | | | | | | Because the PLLs drive global networks, we need to account for already existing and placed SB_GBs when trying to place/pack them. Theses can be user instanciated SB_GBs with BEL attribute, or SB_GB_IOs that got converted during the IO packing. This patch assumes that: - If a PLL is used the output A global network is always used, even if there is no connection to the global output pin - If a PLL with a singe output is used, then the B output global network is still free to be used by whatever. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: During IO packing, remove any unused input connectionSylvain Munaut2019-04-111-0/+13
| | | | | | | | | This is mostly for the benefit of PLL placement because the D_IN_x ports are used for other purposes when PLL is enabled so we need to make sure nothing is connected there already. (even an unused net is too much) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Don't constrain to a PLL bel that has already been usedDavid Shah2019-04-011-0/+2
| | | | | | Fixes #258 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-255-1/+112
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add --placer option and refactor placer selectionDavid Shah2019-03-243-6/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add PlacerHeapCfgDavid Shah2019-03-221-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Make HeAP placer optionalDavid Shah2019-03-222-5/+11
| | | | | | | | | | | | | A CMake option 'BUILD_HEAP' (default on) configures building of the HeAP placer and the associated Eigen3 dependency. Default for the iCE40 is SA placer, with --heap-placer to use HeAP Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for large ECP5 designs and HeAP tends to give better QoR. --sa-placer can be used to use SA instead, and auto-fallback to SA if HeAP not built. Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add TAUCS wrapper and integrationDavid Shah2019-03-221-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add examples folder including floorplan exampleDavid Shah2019-03-2211-0/+42
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Python helper functions for floorplanningDavid Shah2019-03-221-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix u4k in external chipdb mode.Marcin Kościelnicki2019-03-191-3/+3
| | | | Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
* ice40: u4k merge fixDavid Shah2019-02-251-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #239 from YosysHQ/dsp_casc_dummy_wiresDavid Shah2019-02-252-0/+24
|\ | | | | ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
| * ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O portsDavid Shah2019-02-212-0/+24
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: support u4kSimon Schubert2019-02-2313-13/+57
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* ice40: Fix timing class of 'padin' GB outputsDavid Shah2019-02-201-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+8
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| * ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| | | | | | | | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me>
| * ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
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* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-83/+114
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* Merge pull request #220 from YosysHQ/coi3Eddie Hung2019-01-291-6/+9
|\ | | | | ice40: Add budget override for CO->I3 path
| * [ice40] Refactor Arch::getBudgetOverride()Eddie Hung2019-01-291-29/+9
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| * ice40: Add budget override for CO->I3 pathDavid Shah2019-01-271-0/+23
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Path related fixesDavid Shah2019-01-272-6/+33
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
|\ | | | | ice40/pack: Copy attributes to packed cell
| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
| | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
|/ | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add timing data for all IO modesDavid Shah2019-01-072-3/+67
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Improve handling of unconstrained IODavid Shah2018-12-263-3/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-202-4/+45
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ci: Add attosoc smoketest for ice40David Shah2018-12-088-0/+3185
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #163 from daveshah1/timing_optDavid Shah2018-12-073-2/+17
|\ | | | | Adding criticality calculation and experimental timing optimisation pass
| * timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * timing_opt: Improve heuristicsDavid Shah2018-12-061-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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