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* ice40/pack: During IO packing, remove any unused input connectionSylvain Munaut2019-04-111-0/+13
| | | | | | | | | This is mostly for the benefit of PLL placement because the D_IN_x ports are used for other purposes when PLL is enabled so we need to make sure nothing is connected there already. (even an unused net is too much) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Don't constrain to a PLL bel that has already been usedDavid Shah2019-04-011-0/+2
| | | | | | Fixes #258 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-1/+18
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
|\ | | | | ice40/pack: Copy attributes to packed cell
| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
| | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
|/ | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Improve handling of unconstrained IODavid Shah2018-12-261-3/+0
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
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* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
|\ | | | | ice40: raise CE global promotion threshold
| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
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* | ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
| | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Finer-grained control of global promotionDavid Shah2018-11-271-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
| | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40/pll: Fix typo when testing for global port output netSylvain Munaut2018-11-201-1/+1
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-2/+33
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add global network output support for LFOSC/HFOSCSylvain Munaut2018-11-191-2/+10
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Add helper to constain cells that are unique in the FPGASylvain Munaut2018-11-191-0/+16
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-8/+25
| | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-191-40/+23
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-1/+28
| | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
| | | | | | | - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
| | | | | | | Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* timing: Add support for clock constraintsDavid Shah2018-11-121-0/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-09-301-15/+23
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-251-1/+1
|\ | | | | ice40: Adding LVDS input support
| * ice40: Tristate IO support fixesDavid Shah2018-09-241-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #76 from YosysHQ/plloutglobal_fixClifford Wolf2018-09-251-2/+36
|\ \ | | | | | | Add needed PLLOUTGLOBAL ports and mapped it
| * | Added required checks for PLL and fixed messages eolMiodrag Milanovic2018-09-191-3/+31
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| * | Add needed PLLOUTGLOBAL ports and mapped it properlyMiodrag Milanovic2018-09-121-0/+6
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* / ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: make PLL packing more robustSergiusz Bazanski2018-08-191-11/+26
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* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixing constraint placement bugsDavid Shah2018-08-031-2/+3
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Reworking packer and placer to use new generic rel legaliserDavid Shah2018-08-031-0/+3
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
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