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* fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
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* clangformatDavid Shah2018-09-301-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-2/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-2/+0
|\ | | | | Use settings for placer1 and router1
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-2/+0
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* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-18/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
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| * Add pip locationsClifford Wolf2018-08-091-1/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵Eddie Hung2018-08-101-1/+1
|/ | | | std::array
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-10/+11
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-10/+10
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-4/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * clangformatEddie Hung2018-08-061-6/+8
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| | * Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+2
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| | * Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-051-1/+1
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| * | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-081-47/+46
| |\ \ | | | | | | | | | | | | | | | | | | | | # Conflicts: # ecp5/main.cc # ice40/main.cc
| * | | Added project loaderMiodrag Milanovic2018-08-061-0/+1
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* | | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-10/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-19/+13
| |/ / |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-1/+1
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* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-46/+45
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-08-051-12/+12
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* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-2/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-0/+2
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| * clangformatDavid Shah2018-08-041-1/+0
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Add constraint weight as a command line optionDavid Shah2018-08-031-0/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Proper ice40 wire typesClifford Wolf2018-08-031-1/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-031-8/+30
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #22 from YosysHQ/routethruClifford Wolf2018-08-031-1/+11
|\ | | | | Add iCE40 LUT route-through pips
| * Add LUT route-through pips to iCE40 architecture databaseClifford Wolf2018-08-021-1/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40: Use real cell timingsDavid Shah2018-08-021-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Adding cell timings to chipdbDavid Shah2018-08-021-0/+15
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Remove getFrameDecal() APIClifford Wolf2018-08-011-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'redist_slack' into 'master'David Shah2018-08-011-0/+2
|\ | | | | | | | | Update budgets throughout placement and routing See merge request SymbioticEDA/nextpnr!16
| * Modify the getNetinfo*() functions and getBudgetOverride() to not useEddie Hung2018-07-311-1/+1
| | | | | | | | user_idx and to take a PortRef& instead
| * Merge remote-tracking branch 'origin/estdelay' into redist_slackEddie Hung2018-07-311-0/+1
| |\ | | | | | | | | | | | | | | | | | | Conflicts: ecp5/arch.cc generic/arch.cc ice40/arch.cc
| | * Modify predictDelay signatureEddie Hung2018-07-301-1/+1
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| | * Add predictDelay Arch APIClifford Wolf2018-07-301-0/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'redist_slack' into 'redist_slack'Eddie Hung2018-07-311-0/+1
| |\ \ | | | | | | | | | | | | # Conflicts: # common/timing.cc
| | * | getBudgetOverride() now handles COUT crossing tilesEddie Hung2018-07-261-1/+1
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| | * | Revert "Remove Arch::getBudgetOverride()"Eddie Hung2018-07-261-0/+1
| | |/ | | | | | | | | | This reverts commit 749dae4ae5b2b719237af5db28e98ff671bae265.
* | / clangformatSergiusz Bazanski2018-08-011-2/+2
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* | getChipName() should be constClifford Wolf2018-07-311-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add binary search to getBelPinWire() and getBelPinType()Clifford Wolf2018-07-311-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use DelayInfo for cell timing instead of delay_tDavid Shah2018-07-301-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add iCE40 fast/slow delay fields to chipdbClifford Wolf2018-07-301-2/+15
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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