iCE40/nextpnr - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	gowin: add initial PLL support	YRabbit	2022-11-10	1	-0/+4
\| \| \| \| \| \| \| \| \| \| \|	The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
*	gowin: fix compilation	YRabbit	2022-07-19	1	-8/+0
\| \| \| \|	Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
*	gowin: Remove incomprehensible names of the muxes	YRabbit	2022-07-19	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \|	There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
*	WIP shadowram	Pepijn de Vos	2022-06-05	1	-0/+8
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*	gowin: Add ALU support.	YRabbit	2021-10-22	1	-0/+2
\| \| \| \| \| \| \| \|	- Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
*	gowin: add support for wide LUTs.	YRabbit	2021-10-07	1	-0/+34
\| \| \| \| \| \| \| \| \|	* A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
*	Fixing old emails and names in copyrights	gatecat	2021-06-12	1	-1/+1
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Using hashlib in arches	gatecat	2021-06-02	1	-1/+1
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Gowin target (#542)	Pepijn de Vos	2020-12-30	1	-0/+94
	* load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI