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* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
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* Further condenseRoss Schlaikjer2020-04-291-11/+10
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* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
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* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
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* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use dedicated routing for ECLKs where possibleDavid Shah2020-04-141-1/+80
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add TRELLIS_PROGRAM_PREFIXMiodrag Milanovic2020-04-111-4/+6
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* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-073-4/+33
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
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| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
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| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
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| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-073-19/+23
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-073-8/+16
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| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
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* | Merge pull request #419 from garytwong/handle-opendrainDavid Shah2020-04-071-0/+3
|\ \ | | | | | | Handle OPENDRAIN attribute.
| * | Handle OPENDRAIN attribute.Gary Wong2020-04-031-0/+3
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* | | Fix assertion failure on invalid LOCATE input.Gary Wong2020-04-051-0/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to parse this invalid LPF syntax: LOCATE COMP "a" SITE "A1" IOBUF PORT "a" IO_TYPE=LVCMOS33; (note missing semicolon on first line) gives an assertion failure in strip_quotes, because the fifth token is scanned as "A1"IOBUF (without a trailing quote). Avoid the problem by detecting extraneous input and issuing a more specific error.
* | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pinDavid Shah2020-04-031-0/+10
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Remove comment about the USRMCLK primitive being untested.Gary Wong2020-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested and verified working: the trivial configuration: module USRMCLK( USRMCLKI, USRMCLKTS ); input USRMCLKI, USRMCLKTS; endmodule module top( input clk ); reg[ 24:0 ] count = 0; always @( posedge clk ) begin count <= count + 1'b1; end USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) ); endmodule produces the expected output (toggling at high frequency, toggling tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate clock. See https://bayimg.com/AAnNKAAGO for an example. The top (magenta) trace is the MCLK line.
* | Enum/int compatibility for EHXPLLL parametersMartin2020-04-021-2/+7
| | | | | | | | | | | | - Lattice component EHXPLLL parameter compatibility, allowing to pass an int parameter for the enum (as expected by trellis tile) e.g. CLKOP_TRIM_DELAY : integer := 0;
* | ecp5: Proper support for '12k' deviceDavid Shah2020-03-134-7/+21
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #400 from YosysHQ/dave/tri-fixesDavid Shah2020-03-101-1/+16
|\ | | | | Improve handling of unused inout port bits
| * Improve handling of unused inout port bitsDavid Shah2020-02-251-1/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Fix differential inputsDavid Shah2020-03-081-1/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | build: Default the ECP5 and iCE40 roots to the install prefixSylvain Munaut2020-03-031-2/+2
|/ | | | | | | | | If the user specifies a custom install prefix, chances are icestrom/trellis are also in that prefix rather than the hardcoded /usr/local Fixes #351 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Rename cmake path variable TRELLIS_ROOT to TRELLIS_INSTALL_PREFIXSebastian Birke2020-02-041-6/+6
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* CMake: Changing the definition of TRELLIS_ROOT to point to root of lib, ↵Jared Boone2020-02-041-5/+5
| | | | | | | | | share containing trellis libs and data two other commit message of squashed commits: CMake: Search for user lib inside trellis instead of libtrellis CMake: Fix missing path component for share contents
* Merge pull request #391 from YosysHQ/router2-upstreamDavid Shah2020-02-043-7/+85
|\ | | | | Upstreaming router2
| * router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Allow selection of router algorithmDavid Shah2020-02-032-2/+18
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * router2: Make magic numbers configurableDavid Shah2020-02-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Improve bounding box accuracyDavid Shah2020-02-032-10/+34
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: router2 main renameDavid Shah2020-02-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Router2 test integrationDavid Shah2020-02-032-1/+39
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #385 from YosysHQ/router1-arc-fixesDavid Shah2020-02-031-1/+2
|\ \ | |/ |/| Fixes for partial reconfig demo
| * ecp5: Don't reroute existing globalsDavid Shah2020-01-201-1/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | python: Expose PlaceStrength enum and isValidBelForCell on ecp5Erika2020-01-261-0/+3
| | | | | | | | Signed-off-by: Erika <rrika9@yahoo.com>
* | ecp5: Fix tieoff of unused DELAY signalsDavid Shah2020-01-211-3/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add SPICB0 IO supportDavid Shah2020-01-202-3/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Few more caught by clangMiodrag Milanovic2020-01-181-4/+0
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* Merge pull request #382 from YosysHQ/ecp5-psuedodiffDavid Shah2020-01-163-13/+42
|\ | | | | ecp5: Add support for top pseudo diff outputs
| * ecp5: Add support for top pseudo diff outputsDavid Shah2020-01-153-13/+42
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | More adjustments to .bba file locationsLarry Doolittle2020-01-141-1/+1
|/ | | | | | | | | | Follows PM discussion with Marcus Comstedt. Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases, so all cases become compatible with read-only access to git tree. Only known down-side is inefficiency when building out-of-tree for multiple architectures; people following that use case should consider using PREGENERATED_BBA_PATH. It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake, but that would have to be addressed by someone more skilled in Cmake and MSVC.
* Remove barrier to out-of-tree buildsLarry Doolittle2020-01-121-2/+1
| | | | | With this change, nextpnr can build successfully (and run correctly) using the git tree as a read-only reference. No change in behavior observed for in-tree builds.
* clangformatMiodrag Milanovic2019-12-281-16/+24
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