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* cmake: Make HeAP placer always-enabledgatecat2023-03-171-10/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Update GUI rendering to match arch changesgatecat2023-03-161-25/+81
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-03-161-66/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ctmyrtle2023-02-131-12/+156
|\ | | | | ecp5: Propagate clock constraints through DCSC
| * streamline constant_net detectionrowanG0772023-02-061-2/+4
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| * ecp5: DSCS clock propagation if modesel is 0 constantrowanG0772023-02-061-52/+99
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| * ecp5: Propagate clock constraints through DSCSrowanG0772023-02-011-12/+107
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* | ecp5: Handle the case where both CE are the same constantgatecat2023-02-091-2/+8
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: LOCATE in LPF works on singleton vectorrowanG0772023-01-311-1/+8
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* Merge pull request #1084 from YosysHQ/gatecat/ecp5-ioff-fixmyrtle2023-01-271-8/+24
|\ | | | | ecp5: Improve IOFF CE handling robustness
| * ecp5: Improve IOFF CE handling robustnessgatecat2023-01-251-8/+24
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2023-01-251-62/+38
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing <set> includesgatecat2023-01-202-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-044-0/+280
| | | | | | | | | | | | | | | | | | Each DSP block contains two slices, and each slice contains multiple MULT18X18D and ALU54B units. Each unit configures each register to use any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are connected per unit (so for example, two MULTs in the same block could connect their CLK0s to different external signals). However, the hardware only has one actual port per block, so it's required that all CLK0 signals within a block are the same. Because the packer is in general allowed to combine two unrelated units into one block, it may end up combining units that use different signals for the same port, which would eventually have caused a router failure. This commit adds validity checks which ensure only unique signals are used per block, and adds remapping so that conflicting signals are automatically reassigned when possible and required.
* Include ALU54B in cell types with wire location overridesAdam Greig2023-01-041-1/+1
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* ecp5: Improve error handling for missing end-"gatecat2023-01-021-9/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove deprecated functionsMiodrag Milanovic2022-12-221-3/+3
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* ecp5: Only write bitstream if --textcfg passedgatecat2022-12-171-5/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Fix Python bindings for pip iteratorsgatecat2022-11-281-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split bitstream generation into more functionsgatecat2022-09-151-1347/+1402
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-211-2/+2
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* refactor: Use IdString::in instead of || chainsgatecat2022-08-109-123/+89
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-102-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2022-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0712-1348/+1136
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* ecp5: Fix double-counting of FFs in reportgatecat2022-03-161-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: accept lowercase characters in hex strings.Maya2022-03-111-1/+1
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* ecp5: verify hex strings contain only valid characters.Maya2022-03-111-1/+6
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* Merge pull request #925 from YosysHQ/gatecat/netlist-ivgatecat2022-03-013-46/+39
|\ | | | | Switch to potentially-sparse net users array
| * Switch to potentially-sparse net users arraygatecat2022-02-273-46/+39
| | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Fix PDPW16K clock param renaminggatecat2022-02-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-185-238/+238
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-1611-1318/+1674
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-85/+79
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-163-63/+36
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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-14/+9
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: LUT permutation supportgatecat2021-12-137-7/+117
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-132-14/+15
| | | | This reduces the final binary size by ~7 MB for 85k
* clangformatgatecat2021-12-121-4/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use a vector rather than dictMatt Johnston2021-12-123-14/+106
| | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix mistype.YRabbit2021-09-291-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-08-241-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #798 from kleinai/extref-locgatecat2021-08-191-6/+44
|\ | | | | Make EXTREFB handling more robust
| * Make EXTREFB handling more robustAidan Klein2021-08-181-6/+44
| | | | | | | | | | Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA. Also adds location constraints specifically for EXTREFB.
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