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* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
* | Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
* | add more pipsMiodrag Milanovic2019-12-011-0/+49
* | Handle H00 and V00Miodrag Milanovic2019-11-111-6/+49
* | More pips and fix for V01Miodrag Milanovic2019-11-111-42/+170
* | cleanupMiodrag Milanovic2019-11-111-174/+78
* | proper h06 and v06Miodrag Milanovic2019-11-111-34/+39
* | More pips addedMiodrag Milanovic2019-11-101-41/+200
* | more pips, and valid mappingMiodrag Milanovic2019-11-102-10/+23
* | Fixed V2, some more pipsMiodrag Milanovic2019-11-101-12/+43
* | more pipsMiodrag Milanovic2019-11-101-2/+43
* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-093-31/+58
* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-253-13/+105
* | display horizontal wires, add some globals to listMiodrag Milanovic2019-10-234-1/+123
* | Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-203-268/+304
* | type needs to be part of hash for GroupIdMiodrag Milanovic2019-10-201-1/+3
* | muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
* | Remove not used lineMiodrag Milanovic2019-10-201-2/+0
* | Simplify layout of elementsMiodrag Milanovic2019-10-204-400/+254
* | fix slice wireMiodrag Milanovic2019-10-201-20/+20
* | bound signalsMiodrag Milanovic2019-10-201-0/+65
* | more wires between switchboxesMiodrag Milanovic2019-10-204-2/+59
* | Add more types of wiresMiodrag Milanovic2019-10-202-177/+221
* | Less types neededMiodrag Milanovic2019-10-202-56/+24
* | finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
* | wd wiresMiodrag Milanovic2019-10-202-1/+32
* | Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
* | Add output wiresMiodrag Milanovic2019-10-201-0/+35
* | fix mux displayMiodrag Milanovic2019-10-201-2/+2
* | set wire active flagMiodrag Milanovic2019-10-202-1/+3
* | clk and lsr muxesMiodrag Milanovic2019-10-202-1/+93
* | draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-202-7/+106
* | OptimizeMiodrag Milanovic2019-10-202-18/+87
* | Add other side of slice wiresMiodrag Milanovic2019-10-202-14/+118
* | Display rest of slice input wiresMiodrag Milanovic2019-10-202-3/+69
* | Start adding visible wiresMiodrag Milanovic2019-10-205-10/+99
* | Added type to wireMiodrag Milanovic2019-10-203-1/+87
* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-204-28/+157
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* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
* ecp5: Add support for IO registersDavid Shah2019-10-092-0/+103
* ecp5: Add IDDR71B supportDavid Shah2019-10-092-3/+16
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
* ecp5: Preparations for new IO belsDavid Shah2019-10-093-1/+16
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-014-19/+96
* Merge pull request #332 from YosysHQ/dave/python-refactorDavid Shah2019-09-191-96/+2
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| * python: Refactor out bindings shared between ECP5 and iCE40David Shah2019-09-151-96/+2
* | Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-p...David Shah2019-09-191-18/+31
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| * | ecp5: add support for PREGENERATED_BBA_PATHSean Cross2019-09-171-18/+31
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