Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ecp5: Add 10% safety margin to pip delays | David Shah | 2018-11-16 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: clangformat timing changes | David Shah | 2018-11-16 | 3 | -17/+18 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Use speed-grade-specific delay estimate | David Shah | 2018-11-16 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix db import, improve timing data debugging | David Shah | 2018-11-16 | 3 | -4/+40 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Allow selection of device speed grade | David Shah | 2018-11-16 | 1 | -3/+26 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Post-rebase fix | David Shah | 2018-11-16 | 1 | -3/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Consider fanout when calculating pip delays | David Shah | 2018-11-16 | 1 | -2/+12 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix timing pip classes | David Shah | 2018-11-16 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Use new timing data | David Shah | 2018-11-16 | 4 | -94/+82 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix timing data import | David Shah | 2018-11-16 | 1 | -5/+16 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding real timing data to database | David Shah | 2018-11-16 | 6 | -49/+202 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat | David Shah | 2018-11-16 | 2 | -172/+342 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #119 from cr1901/win-fix | David Shah | 2018-11-16 | 4 | -2/+6 |
|\ | | | | | nextpnr-ecp5 Windows Fixes | ||||
| * | Use native PATH environment-variable separator on Windows for PYTHONPATH. ↵ | William D. Jones | 2018-11-03 | 1 | -0/+4 |
| | | | | | | | | | | | | Fixes 'Bad address' error in cmake. Signed-off-by: William D. Jones <thor0505@comcast.net> | ||||
| * | Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with ↵ | William D. Jones | 2018-11-03 | 3 | -2/+2 |
| | | | | | | | | | | | | Windows-provided io.h. Signed-off-by: William D. Jones <thor0505@comcast.net> | ||||
* | | ecp5: Better use of Boost | David Shah | 2018-11-16 | 1 | -3/+3 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Regression fix & format | David Shah | 2018-11-15 | 2 | -4/+14 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Support LOC attribute on DCUs | David Shah | 2018-11-15 | 1 | -1/+25 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Add DCU availability check | David Shah | 2018-11-15 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Add timing info for SERDES | David Shah | 2018-11-15 | 1 | -1/+26 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: DCU clocking fixes | David Shah | 2018-11-15 | 1 | -2/+8 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: EXTREFB fixes | David Shah | 2018-11-15 | 2 | -1/+5 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: clangformat | David Shah | 2018-11-15 | 2 | -18/+23 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Trim IO connected to top level ports | David Shah | 2018-11-15 | 1 | -15/+73 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Adding ancillary DCU bels | David Shah | 2018-11-15 | 4 | -1/+57 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: remove debug and clangformat | David Shah | 2018-11-15 | 3 | -10/+13 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | dcu: Fix bitstream param handling | David Shah | 2018-11-15 | 1 | -0/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Prefer DCCs with dedicated routing when placing DCCs | David Shah | 2018-11-15 | 1 | -0/+43 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Working on DCU | David Shah | 2018-11-15 | 3 | -5/+63 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: DCU bitstream gen handling | David Shah | 2018-11-15 | 2 | -0/+299 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Groundwork for DCU support | David Shah | 2018-11-15 | 3 | -16/+318 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 4 | -3/+11 |
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| * \ | Merge pull request #107 from YosysHQ/router_improve | Eddie Hung | 2018-11-13 | 3 | -2/+10 |
| |\ \ | | | | | | | | | Major rewrite of "router1" | ||||
| | * | | ecp5: Improve delay estimates | David Shah | 2018-11-13 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | Various router1 fixes, Add BelId/WireId/PipId::operator<() | Clifford Wolf | 2018-11-13 | 1 | -0/+4 |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | clangformat | Clifford Wolf | 2018-11-11 | 1 | -8/+2 |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Add getConflictingWireWire() arch API, streamline getConflictingXY semantic | Clifford Wolf | 2018-11-11 | 1 | -5/+10 |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Add getConflictingPipWire() arch API, router1 improvements | Clifford Wolf | 2018-11-11 | 1 | -0/+5 |
| | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Mark getArchOptions as override in derived classes | Pedro Vanzella | 2018-11-13 | 1 | -1/+1 |
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* | | | ecp5: Copy clock constraints during global promotion | David Shah | 2018-11-12 | 1 | -0/+7 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | timing: Add support for clock constraints | David Shah | 2018-11-12 | 1 | -0/+4 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ecp5: EBR clocking fix | David Shah | 2018-11-12 | 1 | -5/+8 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ecp5: Update arch to new timing API | David Shah | 2018-11-12 | 2 | -15/+72 |
|/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Fix 85k PLL_LR | David Shah | 2018-11-11 | 1 | -1/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | show 4th tresllis_io in tile bounds | Miodrag Milanovic | 2018-11-11 | 1 | -1/+1 |
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* | ecp5: Allow setting IO SLEWRATE | David Shah | 2018-11-01 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add PLL support | David Shah | 2018-10-31 | 4 | -7/+168 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Separate global promotion and routing | David Shah | 2018-10-31 | 4 | -33/+87 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add IO buffer insertion | David Shah | 2018-10-31 | 4 | -15/+70 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding LPF parser | David Shah | 2018-10-31 | 3 | -0/+122 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> |