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* ecp5: Fix global clock routing with multiclock DPRAMDavid Shah2019-02-251-3/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router performance improvementsDavid Shah2019-02-251-4/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Implement budget overrides for carry chains and SLICE muxesDavid Shah2019-02-251-2/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve delay modelDavid Shah2019-02-251-3/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Speed up timing analysisDavid Shah2019-02-251-4/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ECLKSYNCB supportDavid Shah2019-02-241-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Packing of ODDRX2FDavid Shah2019-02-241-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Helper functions for DQS and ECLKDavid Shah2019-02-241-0/+37
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add timing data for DQS-related cellsDavid Shah2019-02-241-0/+27
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+22
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| * ecp5: Fix global routing performanceDavid Shah2019-02-121-1/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-091-1/+28
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* ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-081-0/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IOLOGIC timing and bitstream; ODDR workingDavid Shah2018-12-141-0/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding mux support up to LUT6David Shah2018-11-161-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: clangformat timing changesDavid Shah2018-11-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-161-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-161-1/+28
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use new timing dataDavid Shah2018-11-161-77/+59
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding ancillary DCU belsDavid Shah2018-11-151-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Working on DCUDavid Shah2018-11-151-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-2/+2
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-131-2/+2
| |\ | | | | | | Major rewrite of "router1"
| | * ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: EBR clocking fixDavid Shah2018-11-121-5/+8
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Update arch to new timing APIDavid Shah2018-11-121-13/+62
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / show 4th tresllis_io in tile boundsMiodrag Milanovic2018-11-111-1/+1
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* ecp5: Add PLL supportDavid Shah2018-10-311-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding DSP supportDavid Shah2018-10-211-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Implement ECP5 equivalent of c9059fcDavid Shah2018-10-211-0/+9
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-10-161-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-161-3/+27
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add DP16KD timing analysisDavid Shah2018-10-161-2/+29
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Dummy timing entry for BRAMDavid Shah2018-10-051-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-10-011-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Remove broken DRAM timing arcDavid Shah2018-10-011-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-09-291-4/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix global buffer connectivity and timingDavid Shah2018-09-291-0/+12
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Global router produces a working bitstreamDavid Shah2018-09-291-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Integrate global router and debug namingDavid Shah2018-09-291-1/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DCC Bels, fix global router post-rebaseDavid Shah2018-09-291-0/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Helper function and arch tweaks for global routerDavid Shah2018-09-291-0/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: clangformatDavid Shah2018-08-191-27/+19
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix delay heuristicDavid Shah2018-08-191-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add cell delaysDavid Shah2018-08-191-11/+131
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #54 from daveshah1/ecp5_speedupDavid Shah2018-08-191-1/+3
|\ | | | | ecp5: Improving placement speed
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