iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Remove unused advanced timing constraint API	gatecat	2021-02-26	2	-187/+0
*	Allow router2 to use routed but not fixed arcs.	Keith Rothman	2021-02-25	1	-4/+54
*	Fix compiler warnings introduced by -Wextra	gatecat	2021-02-25	3	-6/+6
*	Merge pull request #591 from litghost/add_constant_network	gatecat	2021-02-25	2	-10/+9
\|\
\| *	Remove some signedness warnings.	Keith Rothman	2021-02-23	2	-10/+9
* \|	Merge pull request #597 from litghost/add_dynamic_bitarray	gatecat	2021-02-24	1	-0/+79
\|\ \
\| * \|	Fix some bugs found in review.	Keith Rothman	2021-02-24	1	-5/+2
\| * \|	Add dynamic bitarray to common library.	Keith Rothman	2021-02-23	1	-0/+82
* \| \|	Merge pull request #595 from litghost/const_cell_info	gatecat	2021-02-23	1	-2/+2
\|\ \ \ \| \| \|/ \| \|/\|
\| * \|	Change CellInfo in getBelPinsForCellPin to be const.	Keith Rothman	2021-02-23	1	-2/+2
\| \|/
* \|	Merge pull request #596 from litghost/make_clang_format	gatecat	2021-02-23	2	-11/+16
\|\ \ \| \|/ \|/\|
\| *	Run "make clangformat" to fix new Bits library.	Keith Rothman	2021-02-23	2	-11/+16
* \|	Refactor some common code to CellInfo methods	gatecat	2021-02-23	6	-38/+43
* \|	HeAP: Document legalise_placement_strict better	gatecat	2021-02-23	1	-3/+45
\|/
*	Demote the 'no clocks' warning to info and make clearer	gatecat	2021-02-20	1	-1/+1
*	Merge pull request #592 from YosysHQ/gatecat/rework-delay	gatecat	2021-02-20	7	-35/+98
\|\
\| *	python: Bindings for DelayPair and DelayQuad	gatecat	2021-02-19	1	-0/+25
\| *	Replace DelayInfo with DelayPair/DelayQuad	gatecat	2021-02-19	6	-35/+38
\| *	Add DelayPair and DelayQuad structures	gatecat	2021-02-19	1	-0/+35
* \|	clangformat	gatecat	2021-02-19	1	-1/+2
\|/
*	Merge pull request #576 from litghost/add_cell_bel_pin_mapping	gatecat	2021-02-19	6	-0/+443
\|\
\| *	Use Bits library for bit instrisics.	Keith Rothman	2021-02-17	1	-2/+4
\| *	Refactor "get only from iterator" to a utility.	Keith Rothman	2021-02-17	1	-0/+23
\| *	Working on standing up initial constraints system.	Keith Rothman	2021-02-17	5	-0/+418
* \|	Expose ice40 arch placer-heap internal parameters.	Balint Cristian	2021-02-18	2	-4/+32
\|/
*	Add a Bits utility library.	Keith Rothman	2021-02-17	2	-0/+124
*	Remove isValidBelForCell	gatecat	2021-02-16	4	-24/+38
*	Merge pull request #575 from YosysHQ/gatecat/belpin-2	gatecat	2021-02-15	5	-173/+253
\|\
\| *	router2: Support for multiple bel pins per cell pin	gatecat	2021-02-10	1	-85/+95
\| *	router1: Support for multiple bel pins per cell pin	gatecat	2021-02-10	1	-62/+78
\| *	Start making use of getBelPinsForCellPin API	gatecat	2021-02-10	5	-37/+83
\| *	Add getBelPinsForCellPin to Arch API	gatecat	2021-02-10	1	-0/+8
* \|	Merge pull request #579 from litghost/add_control_for_split_io	gatecat	2021-02-12	1	-0/+1
\|\ \
\| * \|	Add control to whether GenericFrontend splits IO ports.	Keith Rothman	2021-02-11	1	-0/+1
\| \|/
* \|	Make BaseArch getDecalGraphics return an empty range	gatecat	2021-02-12	1	-1/+1
* \|	Merge pull request #580 from litghost/add_design_loaded_state_variable	gatecat	2021-02-12	2	-1/+6
\|\ \
\| * \|	Add design_loaded state variable.	Keith Rothman	2021-02-11	2	-1/+6
\| \|/
* /	Add getBelHidden and add some missing "override" statements.	Keith Rothman	2021-02-11	2	-3/+8
\|/
*	Remove the unused CellInfo::pins field	gatecat	2021-02-10	3	-25/+0
*	Add BaseArchRanges for default ArchRanges types	gatecat	2021-02-09	1	-0/+21
*	Make BaseCtx destructor virtual	gatecat	2021-02-08	1	-1/+1
*	Use 'T' postfix to disambiguate LHS and RHS of using	D. Shah	2021-02-08	1	-42/+48
*	Add archArgs and archArgsToId to Arch API	D. Shah	2021-02-05	1	-0/+3
*	ice40: Switch to BaseArch	D. Shah	2021-02-05	1	-0/+1
*	Add pure-virtual ArchAPI interface	D. Shah	2021-02-05	1	-104/+198
*	Rename ArchBase to BaseArch for consistency with BaseCtx	D. Shah	2021-02-05	1	-1/+1
*	Add default implementation of bel bucket functions	D. Shah	2021-02-05	1	-5/+89
*	Add default implementation of some range-returning functions	D. Shah	2021-02-05	1	-5/+27
*	Add a few more functions to ArchBase	D. Shah	2021-02-05	1	-8/+14
*	ecp5: Use common wire/pip binding	D. Shah	2021-02-05	1	-1/+1