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* Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
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* Add more sanity check for pointersairskywater2022-09-241-0/+1
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* fix runtime segmentation faultairskywater2022-09-241-0/+5
| | | disable null pointer dereference!
* Added the --ignore-rel-clk option to control timing checks for cross-domain ↵Maciej Kurc2022-09-203-115/+108
| | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Code cleanupMaciej Kurc2022-08-311-64/+35
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* add missing overridesMiodrag Milanovic2022-08-221-3/+3
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* pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
| | | | | | | | bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement. Fixes #522 Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-103-4/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* netlist: Add PseudoCell APIgatecat2022-07-087-28/+127
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* generic: Use arch_pybindings_sharedgatecat2022-07-041-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Split up common into kernel,place,routegatecat2022-04-0859-0/+12002
Signed-off-by: gatecat <gatecat@ds0.me>
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