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* Fix crash exiting nextpnr guiMiodrag Milanovic2018-12-061-0/+1
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* Renamed LogLevel members, to prevent issue with system defines on WindowsMiodrag Milanovic2018-12-053-17/+17
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* Merge pull request #165 from smunaut/build_pipeMiodrag Milanović2018-12-051-2/+2
|\ | | | | build: Make use of the pipe option to avoid temporary files
| * build: Make use of the pipe option to avoid temporary filesSylvain Munaut2018-12-041-2/+2
| | | | | | | | | | | | | | | | This is really useful when building the ice40 with the gigantic .cc files that generate multi gigabyte .s temporary files ... this way the assembler just processed it in streaming way. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #166 from ajeakins/masterMiodrag Milanović2018-12-051-0/+1
|\ \ | |/ |/| Fix crash starting the GUI on macOS where we must request a core profile
| * Fix crash starting the GUI on macOS where we must request a core profile.Adrian Jeakins2018-12-041-0/+1
|/ | | | See http://doc.qt.io/qt-5/qabstractopenglfunctions.html
* Merge pull request #162 from whitequark/reset-fanoutDavid Shah2018-12-041-1/+3
|\ | | | | ice40: add reset global promotion threshold
| * ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
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* Merge pull request #160 from dmsc/sb_ledda_ipDavid Shah2018-12-025-1/+26
|\ | | | | ice40: Add support for placing SB_LEDDA_IP block.
| * ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-015-1/+26
|/ | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* Merge pull request #159 from YosysHQ/ecp5_pllplaceDavid Shah2018-12-012-2/+59
|\ | | | | ecp5: Pre-place PLLs and use dedicated routes into globals
| * ecp5: Pre-place PLLs and use dedicated routes into globalsDavid Shah2018-11-302-2/+59
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #158 from YosysHQ/improve_errorDavid Shah2018-11-295-10/+14
|\ \ | |/ |/| Error reporting improvements
| * ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * rulecheck: Improve message printed at startDavid Shah2018-11-291-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Improve reporting of unknown cell typesDavid Shah2018-11-292-2/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * json: Improve reporting of multiple driversDavid Shah2018-11-291-1/+5
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
|\ | | | | ice40: raise CE global promotion threshold
| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
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* | Merge pull request #156 from whitequark/fanoutDavid Shah2018-11-291-7/+11
|\ \ | |/ |/| ice40: print fanout of nets promoted to globals
| * ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
|\ | | | | ice40: Update the way LVDS inputs are handled during bitstream generation
| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #154 from smunaut/issue_141David Shah2018-11-281-72/+212
|\ \ | |/ |/| ice40: Complete rework of the way PLLs are placed and validity checks
| * ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
|/ | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #153 from YosysHQ/global-optionsDavid Shah2018-11-282-3/+14
|\ | | | | ice40: Finer-grained control of global promotion
| * ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #152 from YosysHQ/compile_fixDavid Shah2018-11-271-0/+10
|\ | | | | Fix compile on GCC 5.5 or older
| * Fix compile on GCC 5.5 or olderMiodrag Milanovic2018-11-271-0/+10
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* Merge pull request #150 from YosysHQ/err_warn_countDavid Shah2018-11-264-2/+19
|\ | | | | Print warning and error count at end of execution
| * Print warning and error count at end of executionDavid Shah2018-11-264-2/+19
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: Improve clock constraint log outputDavid Shah2018-11-261-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #149 from smunaut/issue_148David Shah2018-11-264-10/+43
|\ | | | | Fixes for global promotion
| * ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
| | | | | | | | | | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-262-2/+8
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * placer1: During initial placement, don't rip-up strongly binded cellsSylvain Munaut2018-11-261-2/+3
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Update README.mdDavid Shah2018-11-261-4/+6
| | | | | | Fixes #74 Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-11-261-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
|\ | | | | ecp5: Adding support for LUT extension muxes up to LUT7
| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #138 from YosysHQ/refactor_logDavid Shah2018-11-268-123/+84
|\ \ | | | | | | Tidy up logging code, add log file support, make timing failures non-fatal errors
| * | Add nonfatal error support and use for timing failuresDavid Shah2018-11-264-3/+14
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Change the log level of some timing-related messagesDavid Shah2018-11-213-16/+20
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Refactor log code and add log file supportDavid Shah2018-11-215-106/+52
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #139 from YosysHQ/fix_117David Shah2018-11-261-1/+6
|\ \ \ | | | | | | | | router1: Fix unrouted, undriven nets
| * | | router1: Fix unrouted, undriven netsDavid Shah2018-11-211-1/+6
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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