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* Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some utility methods for site instance access.Keith Rothman2021-02-183-13/+42
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update README's with latest instructions and features.Keith Rothman2021-02-183-20/+94
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update tests library to include Bits unit test.Keith Rothman2021-02-171-0/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add utility targets for getting plain text outputs.Keith Rothman2021-02-171-1/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add IOSTANDARD to ports.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Emit fixed attributes to output physical netlist.Keith Rothman2021-02-171-8/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use Bits library for bit instrisics.Keith Rothman2021-02-171-2/+4
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-174-12/+32
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Keep all build artifacts under create_bba/build.Keith Rothman2021-02-172-4/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change how package pin IO sites are selected.Keith Rothman2021-02-173-16/+52
| | | | | | | The first site type that matches is now selected, under the premise that the early site types are more general. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change makefiles to build a FPGA interchange BBA.Keith Rothman2021-02-174-16/+106
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add examples invoking FPGA interchange nextpnr.Keith Rothman2021-02-1711-0/+152
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-176-23/+97
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-174-6/+813
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-178-25/+886
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #589 from litghost/add_bits_librarygatecat2021-02-172-0/+124
|\ | | | | Add a Bits utility library.
| * Add a Bits utility library.Keith Rothman2021-02-172-0/+124
|/ | | | | | | This library captures use of __builtin_popcount and __builtin_ctz on GCC/clang and hopefully handles the MSVC case. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update docs/archapi.mdgatecat2021-02-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #587 from YosysHQ/gatecat/generic-vccgatecat2021-02-172-5/+7
|\ | | | | generic: Don't generate Vcc if not needed
| * generic: Don't generate Vcc if not neededgatecat2021-02-172-5/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-171-3/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-172-13/+274
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
| * Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-162-13/+266
| | | | | | | | | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #585 from YosysHQ/gatecat/remove-ivbfcgatecat2021-02-1724-287/+170
|\ \ | |/ |/| Remove isValidBelForCell
| * Remove isValidBelForCellgatecat2021-02-1624-287/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* | Bump test submodulegatecat2021-02-161-0/+0
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #583 from litghost/add_fpga_interchange_front_and_backendgatecat2021-02-1611-7/+909
|\ | | | | Add FPGA interchange front and backend
| * Pull in fix for out of source builds.Keith Rothman2021-02-151-0/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Move CMake logic into fpga-interchange-schema.Keith Rothman2021-02-152-13/+1
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Small fixes from review.Keith Rothman2021-02-152-2/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add libcapnp-dev for FPGA interchange compilation support.Keith Rothman2021-02-151-1/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add FPGA interchange frontend and backend.Keith Rothman2021-02-157-5/+915
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add interchange schema 3rdparty.Keith Rothman2021-02-152-0/+3
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #584 from YosysHQ/gatecat/generic-belpingatecat2021-02-157-5/+40
|\ | | | | Add bel pin mapping control to nextpnr-generic
| * generic: Update docsgatecat2021-02-151-2/+10
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * generic: Add bel pin mapping testgatecat2021-02-152-0/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * generic: Add APIs for controlling cell->bel pin mappinggatecat2021-02-154-3/+29
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #578 from YosysHQ/machxo2-rebasegatecat2021-02-1538-3/+4511
|\ | | | | machxo2, rebased and updated
| * ci: Bump prjtrellis versiongatecat2021-02-121-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Fix bad rebasegatecat2021-02-121-2/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Misc tidying upgatecat2021-02-122-8/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Python bindings and stub GUIgatecat2021-02-129-6/+346
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Use snake_case for non-ArchAPI functionsgatecat2021-02-124-63/+63
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Use IdStringLists in earnestgatecat2021-02-122-76/+70
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Update with Arch API changesgatecat2021-02-129-468/+119
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * machxo2: Prepare README.md for first PR.William D. Jones2021-02-121-4/+36
| |
| * machxo2: Add prefix parameter to simtest.sh. Remove show command fromWilliam D. Jones2021-02-123-40/+43
| | | | | | | | simtest.sh. Update README.md.
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