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* Merge branch 'master' into 'master'Eddie Hung2018-07-2123-689/+1477
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| * Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
| * Merge branch 'router1ng' into 'master'Clifford Wolf2018-07-212-87/+341
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| | * Bugfix in router1: Also bind src_wireClifford Wolf2018-07-211-0/+2
| | * Add final sanity check in router1Clifford Wolf2018-07-211-0/+19
| | * Refactoring of router1Clifford Wolf2018-07-212-87/+320
| * | Map ports to netsMiodrag Milanovic2018-07-211-0/+14
| * | create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
| * | add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
| * | Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
| * | Fix placement bug with VexRiscV reported by John McMasterDavid Shah2018-07-211-2/+3
| * | Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
| * | add only missing netMiodrag Milanovic2018-07-211-3/+6
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| * Fix minor issue in GUI Wire propertiesClifford Wolf2018-07-211-2/+2
| * Change DelayInfo semantics to what we actually needClifford Wolf2018-07-215-16/+38
| * Add getWireDelay APIClifford Wolf2018-07-214-2/+17
| * Fix warnings and statusMiodrag Milanovic2018-07-213-4/+21
| * Made save project work as wellMiodrag Milanovic2018-07-215-11/+46
| * made open project to workMiodrag Milanovic2018-07-211-2/+73
| * fix introduced bugMiodrag Milanovic2018-07-211-0/+2
| * make new context work againMiodrag Milanovic2018-07-201-0/+3
| * Bind wires to netMiodrag Milanovic2018-07-201-629/+637
| * Merge branch 'gridapi' into 'master'David Shah2018-07-206-17/+115
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| | * Add Location APIs to generic archClifford Wolf2018-07-205-24/+49
| | * Improve iCE40 and common Loc codeClifford Wolf2018-07-204-15/+52
| | * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapiClifford Wolf2018-07-2050-872/+911
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| * | Few more checks on parameters and error eolMiodrag Milanovic2018-07-202-7/+17
| * | Start adding bitstream reading for ice40Miodrag Milanovic2018-07-204-43/+143
| * | ice40: Optimise reset/enable net checkingDavid Shah2018-07-203-11/+14
| | * Add Loc struct for x/y/z bel locationsClifford Wolf2018-07-172-2/+38
* | | Merge branch 'master' into 'master'Eddie Hung2018-07-1948-824/+717
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| * | ice40: Trim DSP inputs that are constant where appropriateDavid Shah2018-07-192-2/+10
| * | ice40: Packer and bitstream gen support for MAC16sDavid Shah2018-07-193-3/+111
| * | ice40: Adding cell definition for DSPsDavid Shah2018-07-195-7/+80
| * | ice40: Add virtual padin wires for intoscs and GB_IOsDavid Shah2018-07-191-1/+14
| * | Reducing performance cost of assertsDavid Shah2018-07-192-9/+11
| * | ice40: Adding data for extra cell configurationDavid Shah2018-07-192-4/+39
| * | Fix click on wire in net sectionMiodrag Milanovic2018-07-181-1/+1
| * | cell and net now can be selected, fixed issue with highlightMiodrag Milanovic2018-07-181-19/+15
| * | added clear action for browsing historyMiodrag Milanovic2018-07-184-0/+18
| * | removed not used and buggy featuresMiodrag Milanovic2018-07-1813-474/+0
| * | ecp5: Tidying up examplesDavid Shah2018-07-1810-265/+40
| * | ecp5: Add support for pin name constraints using 'LOC' attributesDavid Shah2018-07-185-15/+64
| * | ecp5: Adding PIO data to chipdbDavid Shah2018-07-182-0/+101
| * | ice40: RenamingDavid Shah2018-07-184-9/+9
| * | ice40: Fixes for inverted clocksDavid Shah2018-07-183-2/+7
| * | Cleanups in iCE40 blinky and picorv32 testsClifford Wolf2018-07-184-35/+2
| * | Add Net/Cell "udata" fieldClifford Wolf2018-07-181-0/+4
| * | ice40: Use xArchArgs in validity checkDavid Shah2018-07-184-39/+39
| * | ice40: Make assignArchArgs a Arch method; call also after legaliserDavid Shah2018-07-184-31/+37