Commit message (Collapse) | Author | Age | Files | Lines | |
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* | gui: Fix some typos | gatecat | 2021-07-25 | 2 | -5/+5 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | gui: Implement about dialog | gatecat | 2021-07-25 | 4 | -0/+15 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #757 from antmicro/lut-mapping-cache | gatecat | 2021-07-22 | 8 | -74/+510 |
|\ | | | | | interchange: Add caching of site LUT mapping solution | ||||
| * | Added an option to disable the LUT mapping cache | Maciej Kurc | 2021-07-22 | 5 | -8/+16 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added more code comments, formatted the code | Maciej Kurc | 2021-07-22 | 6 | -123/+124 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added computing and reporting LUT mapping cache size | Maciej Kurc | 2021-07-16 | 2 | -0/+37 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Fixed assertion typos | Maciej Kurc | 2021-07-16 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Migrated C arrays to std::array containers. | Maciej Kurc | 2021-07-16 | 2 | -9/+31 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | LUT mapping ceche optimizations 2 | Maciej Kurc | 2021-07-16 | 3 | -93/+17 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | LUT mapping cache optimizations 1 | Maciej Kurc | 2021-07-16 | 2 | -32/+48 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Working site LUT mapping cache | Maciej Kurc | 2021-07-16 | 7 | -42/+470 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | | Merge pull request #772 from antmicro/xdc_parse | gatecat | 2021-07-21 | 1 | -0/+7 |
|\ \ | | | | | | | [Interchange] Add dummy function to parse creat_clock in XDC files | ||||
| * | | Add dummy function to parse creat_clock in XDC files | Maciej Dudek | 2021-07-21 | 1 | -0/+7 |
|/ / | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
* | | Merge pull request #768 from YosysHQ/gatecat/fix-gui-error | gatecat | 2021-07-21 | 2 | -11/+62 |
|\ \ | | | | | | | gui: Improve Fatal Error message | ||||
| * | | gui: Improve Fatal Error message | gatecat | 2021-07-20 | 2 | -11/+62 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | | clangformat | gatecat | 2021-07-21 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | | Merge pull request #770 from YosysHQ/gatecat/empty-idstringlist | gatecat | 2021-07-20 | 1 | -1/+1 |
|\ \ \ | | | | | | | | | Fix definition of an empty IdStringList | ||||
| * | | | Fix definition of an empty IdStringList | gatecat | 2021-07-20 | 1 | -1/+1 |
| |/ / | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | | Merge pull request #771 from YosysHQ/gatecat/ice40-ip-no-busaddr74 | gatecat | 2021-07-20 | 1 | -3/+4 |
|\ \ \ | |/ / |/| | | ice40: Use default value when IP is missing BUS_ADDR74 parameter | ||||
| * | | ice40: Use default value when IP is missing BUS_ADDR74 parameter | gatecat | 2021-07-20 | 1 | -3/+4 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #767 from YosysHQ/gatecat/ic-pref-const | gatecat | 2021-07-20 | 1 | -1/+10 |
|\ \ | | | | | | | interchange: Fix preferred constant handling when canInvert | ||||
| * | | interchange: Fix preferred constant handling when canInvert | gatecat | 2021-07-20 | 1 | -1/+10 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | | Merge pull request #766 from pepijndevos/python | gatecat | 2021-07-17 | 2 | -4/+2 |
|\ \ \ | | | | | | | | | Remove python path from gowin target | ||||
| * | | | remove generic leftover in gowin | Pepijn de Vos | 2021-07-17 | 1 | -2/+2 |
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| * | | | remove generic leftover in gowin | Pepijn de Vos | 2021-07-17 | 1 | -2/+0 |
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* | | | Merge pull request #764 from acomodi/fix-pseudo-pips | gatecat | 2021-07-15 | 1 | -8/+18 |
|\ \ \ | |/ / |/| | | interchange: disallow pseudo-pip on same nets if tile has luts | ||||
| * | | interchange: disallow pseudo-pip on same nets if tile has luts | Alessandro Comodi | 2021-07-15 | 1 | -8/+18 |
|/ / | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | | Merge pull request #762 from antmicro/testarch_timing | gatecat | 2021-07-14 | 2 | -2/+2 |
|\ \ | | | | | | | [interchange] Update chipdb and python-fpga-interchange versions | ||||
| * | | [interchange] Update chipdb and python-fpga-interchange versions | Maciej Dudek | 2021-07-14 | 2 | -2/+2 |
|/ / | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
* | | Merge pull request #761 from acomodi/interchange-constrs | gatecat | 2021-07-12 | 5 | -13/+174 |
|\ \ | | | | | | | interchange: add user placement constraints handling | ||||
| * | | interchange: xdc and place constr: address review comments | Alessandro Comodi | 2021-07-12 | 3 | -23/+13 |
| | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | | interchange: xdc: add get_cells command | Alessandro Comodi | 2021-07-12 | 1 | -13/+70 |
| | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | | interchange: add constraints constraints application routine | Alessandro Comodi | 2021-07-12 | 4 | -0/+114 |
|/ / | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | | Merge pull request #760 from YosysHQ/gatecat/xcup-ibufds | gatecat | 2021-07-12 | 2 | -5/+16 |
|\ \ | | | | | | | interchange: Support for UltraScale+ differential input buffers | ||||
| * | | interchange: Skip IO ports in dedicated routing check | gatecat | 2021-07-12 | 1 | -0/+8 |
| | | | | | | | | | | | | | | | | | | These have already been dealt with in arch_pack_io Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: Debug IO port validity check failures | gatecat | 2021-07-12 | 2 | -3/+5 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS | gatecat | 2021-07-12 | 1 | -3/+4 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #759 from pepijndevos/gw1ndb | gatecat | 2021-07-11 | 1 | -1/+8 |
|\ \ | | | | | | | GW1NR is not a seperate family, but GW1NS is | ||||
| * | | GW1NR is not a seperate family, but GW1NS is | Pepijn de Vos | 2021-07-11 | 1 | -1/+8 |
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* | | Merge pull request #758 from YosysHQ/gatecat/hist-oob | gatecat | 2021-07-11 | 1 | -1/+6 |
|\ \ | | | | | | | timing: Fix out-of-bounds histogram bins in all cases | ||||
| * | | timing: Fix out-of-bounds histogram bins in all cases | gatecat | 2021-07-10 | 1 | -1/+6 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge branch 'master' of github.com:YosysHQ/nextpnr | gatecat | 2021-07-10 | 6 | -23/+93 |
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| * \ | Merge pull request #755 from yrabbit/io_port | gatecat | 2021-07-08 | 1 | -16/+24 |
| |\ \ | | | | | | | | | Pin modes parser | ||||
| | * | | Fix the boolean. | YRabbit | 2021-07-08 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| | * | | Fix formating | YRabbit | 2021-07-07 | 1 | -24/+24 |
| | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| | * | | Fix boolean value. | YRabbit | 2021-07-07 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| | * | | Merge branch 'master' into io_port | YRabbit | 2021-07-07 | 18 | -78/+201 |
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| | * | | Wip parser | YRabbit | 2021-07-07 | 1 | -16/+4 |
| | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| | * | | Parser | YRabbit | 2021-07-05 | 1 | -0/+9 |
| | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| | * | | Merge branch 'master' into io_port | YRabbit | 2021-07-03 | 1 | -2/+13 |
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