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* gui: Fix some typosgatecat2021-07-252-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gui: Implement about dialoggatecat2021-07-254-0/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-228-74/+510
|\ | | | | interchange: Add caching of site LUT mapping solution
| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-225-8/+16
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added more code comments, formatted the codeMaciej Kurc2021-07-226-123/+124
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added computing and reporting LUT mapping cache sizeMaciej Kurc2021-07-162-0/+37
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed assertion typosMaciej Kurc2021-07-161-2/+2
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Migrated C arrays to std::array containers.Maciej Kurc2021-07-162-9/+31
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping ceche optimizations 2Maciej Kurc2021-07-163-93/+17
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping cache optimizations 1Maciej Kurc2021-07-162-32/+48
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Working site LUT mapping cacheMaciej Kurc2021-07-167-42/+470
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #772 from antmicro/xdc_parsegatecat2021-07-211-0/+7
|\ \ | | | | | | [Interchange] Add dummy function to parse creat_clock in XDC files
| * | Add dummy function to parse creat_clock in XDC filesMaciej Dudek2021-07-211-0/+7
|/ / | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #768 from YosysHQ/gatecat/fix-gui-errorgatecat2021-07-212-11/+62
|\ \ | | | | | | gui: Improve Fatal Error message
| * | gui: Improve Fatal Error messagegatecat2021-07-202-11/+62
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | clangformatgatecat2021-07-211-1/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #770 from YosysHQ/gatecat/empty-idstringlistgatecat2021-07-201-1/+1
|\ \ \ | | | | | | | | Fix definition of an empty IdStringList
| * | | Fix definition of an empty IdStringListgatecat2021-07-201-1/+1
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #771 from YosysHQ/gatecat/ice40-ip-no-busaddr74gatecat2021-07-201-3/+4
|\ \ \ | |/ / |/| | ice40: Use default value when IP is missing BUS_ADDR74 parameter
| * | ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #767 from YosysHQ/gatecat/ic-pref-constgatecat2021-07-201-1/+10
|\ \ | | | | | | interchange: Fix preferred constant handling when canInvert
| * | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #766 from pepijndevos/pythongatecat2021-07-172-4/+2
|\ \ \ | | | | | | | | Remove python path from gowin target
| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+2
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| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+0
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* | | Merge pull request #764 from acomodi/fix-pseudo-pipsgatecat2021-07-151-8/+18
|\ \ \ | |/ / |/| | interchange: disallow pseudo-pip on same nets if tile has luts
| * | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #762 from antmicro/testarch_timinggatecat2021-07-142-2/+2
|\ \ | | | | | | [interchange] Update chipdb and python-fpga-interchange versions
| * | [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-142-2/+2
|/ / | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #761 from acomodi/interchange-constrsgatecat2021-07-125-13/+174
|\ \ | | | | | | interchange: add user placement constraints handling
| * | interchange: xdc and place constr: address review commentsAlessandro Comodi2021-07-123-23/+13
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: xdc: add get_cells commandAlessandro Comodi2021-07-121-13/+70
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: add constraints constraints application routineAlessandro Comodi2021-07-124-0/+114
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #760 from YosysHQ/gatecat/xcup-ibufdsgatecat2021-07-122-5/+16
|\ \ | | | | | | interchange: Support for UltraScale+ differential input buffers
| * | interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
| | | | | | | | | | | | | | | | | | These have already been dealt with in arch_pack_io Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #759 from pepijndevos/gw1ndbgatecat2021-07-111-1/+8
|\ \ | | | | | | GW1NR is not a seperate family, but GW1NS is
| * | GW1NR is not a seperate family, but GW1NS isPepijn de Vos2021-07-111-1/+8
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* | Merge pull request #758 from YosysHQ/gatecat/hist-oobgatecat2021-07-111-1/+6
|\ \ | | | | | | timing: Fix out-of-bounds histogram bins in all cases
| * | timing: Fix out-of-bounds histogram bins in all casesgatecat2021-07-101-1/+6
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge branch 'master' of github.com:YosysHQ/nextpnrgatecat2021-07-106-23/+93
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| * \ Merge pull request #755 from yrabbit/io_portgatecat2021-07-081-16/+24
| |\ \ | | | | | | | | Pin modes parser
| | * | Fix the boolean.YRabbit2021-07-081-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Fix formatingYRabbit2021-07-071-24/+24
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Fix boolean value.YRabbit2021-07-071-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Merge branch 'master' into io_portYRabbit2021-07-0718-78/+201
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| | * | Wip parserYRabbit2021-07-071-16/+4
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | ParserYRabbit2021-07-051-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Merge branch 'master' into io_portYRabbit2021-07-031-2/+13
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