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* | Merge pull request #1040 from yrabbit/pll-stage0myrtle2022-11-116-8/+210
|\| | | | | gowin: add initial PLL support
| * gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
| | | | | | | | | | | | | | Replacing snprintf() with ctx->idf() in PLL commit, but not yet a complete overhaul. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: add initial PLL supportYRabbit2022-11-106-1/+227
| | | | | | | | | | | | | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warningmyrtle2022-11-101-0/+1
|\ \ | | | | | | Fix "implicit copy constructor for 'Property' is deprecated"
| * | Fix "implicit copy constructor for 'Property' is deprecated"gatecat2022-11-101-0/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* / fabulous: Tweak delay estimategatecat2022-11-101-0/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1037 from YosysHQ/fix_python_verMiodrag Milanović2022-10-241-1/+2
|\ | | | | Fix python version in CI
| * Fix python version in CIMiodrag Milanovic2022-10-241-1/+2
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* Update CI scriptMiodrag Milanovic2022-10-241-6/+6
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* run clangformatgatecat2022-10-172-7/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1034 from lushaylabs/support-windows-crlfmyrtle2022-10-171-4/+4
|\ | | | | Support windows line endings in constraints for nextpnr-gowin
| * support windows line endingsLushay Labs2022-10-091-4/+4
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* | Merge pull request #1035 from tyler274/patch-1myrtle2022-10-171-1/+1
|\ \ | |/ |/| Correct Not Equal operator implementation in ice40
| * Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
|/ | | I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
* Merge pull request #1032 from davidlattimore/registered-output-xformmyrtle2022-10-052-0/+9
|\ | | | | nexus: Transform registered output parameters
| * nexus: Transform registered output parametersDavid Lattimore2022-10-052-0/+9
|/ | | | | | | | | | | | Dual ported: OUTREG_A -> OUT_REGMODE_A OUTREG_B -> OUT_REGMODE_B Pseudo dual ported: OUTREG -> OUT_REGMODE_B Single ported: OUTREG -> OUT_REGMODE_A
* Merge pull request #1031 from YosysHQ/gatecat/fab-nextmyrtle2022-09-305-2/+130
|\ | | | | fabulous: Add support for the CLB muxes
| * fabulous: Pack, validity check and FASM support for muxesgatecat2022-09-304-5/+84
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * fabulous: Add split MUX belsgatecat2022-09-302-1/+50
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fixmyrtle2022-09-261-15/+21
|\ | | | | ice40: Fix handling of carry out route-thru via 25,14
| * ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1029 from airskywater/airskywater-patch-1myrtle2022-09-241-0/+6
|\ | | | | Fix runtime segmentation fault
| * Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
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| * Add more sanity check for pointersairskywater2022-09-241-0/+1
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| * fix runtime segmentation faultairskywater2022-09-241-0/+5
|/ | | disable null pointer dereference!
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-204-11/+300
|\ | | | | Support cross-domain clock relations in timing analyser
| * Added the --ignore-rel-clk option to control timing checks for cross-domain ↵Maciej Kurc2022-09-203-115/+108
| | | | | | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Code cleanupMaciej Kurc2022-08-312-68/+39
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed port timing classes of DCC ports in the Nexus architectureMaciej Kurc2022-08-301-4/+11
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-srcmyrtle2022-09-202-0/+17
|\ \ | | | | | | router2: Reserve source wire, too; ice40 fixes
| * | ice40: implement checkPipAvailForNetgatecat2022-09-201-0/+10
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Reserve source wire, toogatecat2022-09-201-0/+7
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | fabulous: fix, but disable, IO configurationgatecat2022-09-161-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactormyrtle2022-09-161-1347/+1402
|\ \ | | | | | | ecp5: Split bitstream generation into more functions
| * | ecp5: Split bitstream generation into more functionsgatecat2022-09-151-1347/+1402
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-polmyrtle2022-09-161-3/+7
|\ \ \ | | | | | | | | ice40: Fix UltraPlus BRAM clock polarity
| * | | ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixesmyrtle2022-09-153-1/+42
|\ \ \ \ | |_|/ / |/| | | nexus: Add ES2 device names and --list-devices
| * | | nexus: Add ES2 device names and --list-devicesgatecat2022-09-153-1/+42
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaductmyrtle2022-09-1512-1/+1637
|\ \ \ | | | | | | | | fabulous: Add a viaduct uarch
| * | | fabulous: Add a viaduct uarchgatecat2022-09-0912-1/+1637
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1024 from YosysHQ/gatecat/pybind11-bumpmyrtle2022-09-15214-10025/+21644
|\ \ \ \ | |_|/ / |/| | | 3rdparty: Bump vendored pybind11 version for py3.11 support
| * | | 3rdparty: Bump vendored pybind11 version for py3.11 supportgatecat2022-09-14214-10025/+21644
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1018 from yrabbit/bf-0myrtle2022-08-251-0/+2
|\ \ \ | |_|/ |/| | gowin: BUGFIX. Really memorize the chip
| * | gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
|/ / | | | | | | | | | | | | When it really needed to distinguish between the chips, this unforgivable error was discovered :) Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1017 from YosysHQ/routerfixmyrtle2022-08-222-5/+4
|\ \ | | | | | | Router fix
| * | add missing overridesMiodrag Milanovic2022-08-221-3/+3
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| * | Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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