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* Added a commandline option controlled writeout of per-net timing detailsMaciej Kurc2021-09-284-9/+22
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added description of the JSON report structure.Maciej Kurc2021-09-281-1/+73
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Moved timing result report storage to the context, added its writeout to the ↵Maciej Kurc2021-09-286-282/+279
| | | | | | current utilization and fmax report Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added reporting critical paths in JSON formatMaciej Kurc2021-09-281-25/+49
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Decoupled critical path report generation from its printingMaciej Kurc2021-09-281-134/+264
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Switched to JSON format for timing analysis reportMaciej Kurc2021-09-281-33/+81
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added writing a CSV report with timing analysis of each net branchMaciej Kurc2021-09-284-6/+89
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #827 from YosysHQ/gatecat/idstring-ingatecat2021-09-271-0/+10
|\ | | | | idstring: Add 'in' function from Yosys
| * idstring: Add 'in' functiongatecat2021-09-271-0/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #812 from antmicro/MacroCellsgatecat2021-09-277-22/+572
|\ | | | | Convert macros to clusters for better placement
| * Fix small isses and code formattingMaciej Dudek2021-09-275-148/+150
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Break up macro_cluster_placement into smaller functionsMaciej Dudek2021-09-241-20/+33
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Update python-fpga-interchange to v0.0.20Maciej Dudek2021-09-231-1/+1
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Fix AC-3 algorithmMaciej Dudek2021-09-231-9/+17
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Improve macro cluster placementMaciej Dudek2021-09-231-235/+41
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Change Cluster placement algorithmMaciej Dudek2021-09-233-123/+133
| | | | | | | | | | | | | | Use physical placement from device DB It should reduce runtime Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding MacroCell placementMaciej Dudek2021-09-234-21/+353
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding support for MacroCellsMaciej Dudek2021-09-235-6/+385
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* | ci: Bump prjoxide versiongatecat2021-09-241-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #826 from YosysHQ/gatecat/nexus-lutpermgatecat2021-09-246-6/+100
|\ \ | |/ |/| nexus: Add LUT permutation support
| * nexus: Add resource cost overridesgatecat2021-09-242-2/+21
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router2: Allow overriding resource costsgatecat2021-09-242-2/+9
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: LUT permutation supportgatecat2021-09-244-4/+72
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #825 from antmicro/chain_swap_fixgatecat2021-09-231-2/+15
|\ | | | | Fix chain swap
| * Fix chain swapMaciej Dudek2021-09-231-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Issue was due to dest_bels being not cleared between clusters unbindes, causing newly bind bels to be unbinded and having their old bel value changed to new bel value. Then when swap failed 2 cells were being bind to a single bel. I tested leaving dest_bels in the function scope and moving it to the loop scope. Code with dest_bels in the loop scope was faster than leaving it in the function scope, and checking if the cell is in the processed cluster. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #822 from YosysHQ/gatecat/nexus-split-vccgatecat2021-09-233-0/+7
|\ \ | | | | | | nexus: Support for split Vcc routing
| * | nexus: Support for split Vcc routinggatecat2021-09-223-0/+7
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #824 from YosysHQ/gatecat/py-sigintgatecat2021-09-231-1/+7
|\ \ \ | |_|/ |/| | python: Restore SIGINT handler while running a Python script
| * | python: Restore SIGINT handler while running a Python scriptgatecat2021-09-221-1/+7
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaksgatecat2021-09-222-2/+4
|\ \ \ | |/ / |/| | nexus: Tweaks for router1 performance
| * | nexus: Tweaks for router1 performancegatecat2021-09-222-2/+4
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #821 from YosysHQ/gatecat/dsp-fixgatecat2021-09-225-36/+80
|\ \ | |/ |/| nexus: Fix DSP macro placement
| * placer1: Remove redundant relative constraint checkgatecat2021-09-221-4/+0
| | | | | | | | | | | | Macros with potentially inconsistent spacing are now permissible. Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Fix DSP macro placementgatecat2021-09-224-32/+80
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #815 from antmicro/nexus-fix-siologic-handlinggatecat2021-09-202-2/+234
|\ | | | | nexus: Fixed an improved SIOLOGIC handling
| * Added support for syn_useioff for enabling tri-state control FF integration ↵Maciej Kurc2021-09-201-13/+23
| | | | | | | | | | | | into IOLOGIC. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Use correct names for IDDRX1_ODDRX1 FASM featuresMaciej Kurc2021-09-172-22/+4
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added automatic inference and integration of FFs driving T pin into IOLOGICMaciej Kurc2021-09-172-16/+177
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added handling of the case when tri-state control net bypasses SIOLOGIC belMaciej Kurc2021-09-171-2/+81
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | placer1: Fix cluster swap cost updatesgatecat2021-09-181-8/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | timing: Always use max delay for required timegatecat2021-09-181-3/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | timing: Fix slack for unconstrained clocksgatecat2021-09-181-6/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #817 from YosysHQ/gatecat/chain-swapgatecat2021-09-181-47/+105
|\ \ | |/ |/| placer1: Allow swapping chains with other chains
| * placer1: Allow swapping chains with other chainsgatecat2021-09-171-47/+105
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #813 from YosysHQ/gatecat/py-on-failgatecat2021-09-172-1/+16
|\ | | | | command: Allow running Python on failure for state introspection
| * command: Allow running Python on failure for state introspectiongatecat2021-09-162-1/+16
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #806 from yrabbit/extend-placementgatecat2021-09-083-16/+74
|\ | | | | gowin: Add constraints on primitive placement.
| * Merge branch 'master' into extend-placementYRabbit2021-09-081-5/+18
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| * \ Merge branch 'master' into extend-placementYRabbit2021-09-073-4/+12
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| * \ \ Merge branch 'combine-dff' into extend-placementYRabbit2021-09-041-2/+26
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