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| | * | | Merge branch 'master' into combine-dffYRabbit2021-09-024-11/+24
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| | * | | | gowin: Place DFFs of different types in the slice.YRabbit2021-08-311-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the registers of the same type or pairs shown below to be placed in the same slide: |--------|--------| | DFFS | DFFR | | DFFSE | DFFRE | | DFFP | DFFC | | DFFPE | DFFCE | | DFFNS | DFFNR | | DFFNSE | DFFNRE | | DFFNP | DFFNC | | DFFNPE | DFFNCE | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | | | | Merge branch 'master' into extend-placementYRabbit2021-09-044-11/+24
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| * | | | gowin: Add constraints on primitive placement.YRabbit2021-08-313-14/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for the INS_LOC instruction in the constraints file (.CST), which is used to specify object placement. Expanded treatment of IO_LOC/IO_PORT constraints, which now can be applied to both ports and IO buffers. Port constraints have priority. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | | | Merge pull request #808 from acomodi/fix-xdcgatecat2021-09-081-0/+2
|\ \ \ \ \ | |_|_|_|/ |/| | | | interchange: xdc: add more not_implemented commands
| * | | | interchange: xdc: add more not_implemented commandsAlessandro Comodi2021-09-081-0/+2
|/ / / / | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | | | Merge pull request #807 from acomodi/fix-xdcgatecat2021-09-071-5/+18
|\ \ \ \ | |_|_|/ |/| | | interchange: xdc: add common not_implemented function
| * | | interchange: xdc: add common not_implemented functionAlessandro Comodi2021-09-071-5/+18
|/ / / | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | | clangformatgatecat2021-09-061-2/+4
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | router2: Fix uninitialised valuesgatecat2021-09-061-1/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | nexus: Fix getBelGlobalBufgatecat2021-09-021-1/+5
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | router2: Fix explored countgatecat2021-09-021-0/+2
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #790 from acomodi/place-only-same-cluster-in-sitegatecat2021-08-314-11/+24
|\ \ | |/ |/| interchange: place only cells belonging to the same clusters in the same site
| * interchange: clusters: fix other cluster allowance checks in same siteAlessandro Comodi2021-08-311-7/+2
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: entirely disable cache when binding site routingAlessandro Comodi2021-08-311-6/+6
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * gh: interchange: bump python-interchange tagAlessandro Comodi2021-08-311-1/+1
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: disallow placing cells on sites with clustersAlessandro Comodi2021-08-272-4/+22
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* clangformatgatecat2021-08-261-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #805 from YosysHQ/gatecat/py-portref-byvaluegatecat2021-08-261-10/+10
|\ | | | | python: Wrap PortRef by value
| * python: Wrap PortRef by valuegatecat2021-08-261-10/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #710 from Ravenslofty/mistral-mlab-as-labgatecat2021-08-244-50/+85
|\ | | | | mistral: Use MLABs as if they're LABs (for now)
| * mistral: Permute MLAB init bits correctlygatecat2021-08-241-0/+22
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| * mistral: Use MLABs as if they're LABs (for now)Lofty2021-08-174-50/+63
| | | | | | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com>
* | clangformatgatecat2021-08-241-5/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #801 from yrabbit/TRBL-stylegatecat2021-08-231-5/+37
|\ \ | | | | | | gowin: Add the IO[TRBL]style placement recognition
| * | gowin: Add the IO[TRBL]style placement recognitionYRabbit2021-08-231-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Specifying pin placement with this notation (e.g. IOR4B) allows to use the same constraint file without changes for different packages and even different families. The vendor router also understands this notation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | Merge pull request #802 from YosysHQ/gatecat/python-rt-dlygatecat2021-08-232-0/+13
|\ \ \ | |/ / |/| | python: Allow querying route delays
| * | python: Allow querying route delaysgatecat2021-08-232-0/+13
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #798 from kleinai/extref-locgatecat2021-08-191-6/+44
|\ \ | | | | | | Make EXTREFB handling more robust
| * | Make EXTREFB handling more robustAidan Klein2021-08-181-6/+44
| | | | | | | | | | | | | | | Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA. Also adds location constraints specifically for EXTREFB.
* | | Merge pull request #800 from smunaut/fix_py_portrefvectorgatecat2021-08-191-0/+2
|\ \ \ | |_|/ |/| | pybindings: Fix mapping for PortRefVector
| * | pybindings: Fix mapping for PortRefVectorSylvain Munaut2021-08-191-0/+2
|/ / | | | | | | | | | | | | | | | | | | This is used by net.users for instance. Removed by mistake in 4ac00af6fadc0405867fdac84229d2cda390c108 Fixes #799 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #794 from YosysHQ/gatecat/router2p5gatecat2021-08-163-432/+444
|\ \ | | | | | | router2: Improved bidir routing and timing-driven ripup option
| * | router2: Add experimental timing-driven ripup optiongatecat2021-08-153-14/+67
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Alternative congestion cost schedulegatecat2021-08-151-1/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Adding some criticality heuristicsgatecat2021-08-151-13/+29
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Improved bidir routing and data structuresgatecat2021-08-151-415/+358
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #795 from YosysHQ/gatecat/mistral-include-fixgatecat2021-08-153-3/+3
|\ \ | | | | | | mistral: Include mistral generated files in include dirs
| * | mistral: Include mistral generated files in include dirsgatecat2021-08-153-3/+3
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | mistral: Fix pip binding checkgatecat2021-08-141-4/+11
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-08-141-2/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #793 from gregdavill/ecp5_diff_odgatecat2021-08-141-1/+13
|\ \ | |/ |/| ecp5: Enable OPENDRAIN on differential outputs
| * ecp5: Enable OPENDRAIN on differential outputsGreg Davill2021-08-141-1/+13
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* Merge pull request #791 from yrabbit/wipgatecat2021-08-062-7/+14
|\ | | | | gowin: Add support for IOBUF and TBUF I/O modes. Change the constraint parser.
| * gowin: Change the constraint parser to support multiple options per line. ↵YRabbit2021-08-062-7/+14
|/ | | | | | Add support for IOBUF and TBUF I/O modes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #789 from YosysHQ/gatecat/ecp5-pdp-outreggatecat2021-08-031-1/+4
|\ | | | | ecp5: Copy REGMODE in PDP mode to both A and B ports
| * ecp5: Copy REGMODE in PDP mode to both A and B portsgatecat2021-08-021-1/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #787 from YosysHQ/gatecat/reportgatecat2021-07-309-1/+136
|\ | | | | Add JSON utilisation and timing report
| * common: Add JSON timing and utilisation reportgatecat2021-07-294-0/+105
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * basectx: Add a field to store timing resultsgatecat2021-07-295-1/+31
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 22:35:53 +0000