| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | bump interchange schema | Alessandro Comodi | 2021-05-20 | 1 | -0/+0 | |
| | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | |||||
| | * | interchange: phys: add site instance idstr for pseudo tile PIPs | Alessandro Comodi | 2021-05-19 | 1 | -0/+19 | |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | |||||
| * | Run clangformat | gatecat | 2021-05-16 | 3 | -6/+8 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | Merge pull request #708 from Ravenslofty/mistral-getchipname | gatecat | 2021-05-15 | 1 | -1/+1 | |
| |\ | | | | | mistral: add getChipName | |||||
| | * | mistral: add getChipName | Lofty | 2021-05-15 | 1 | -1/+1 | |
| |/ | | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com> | |||||
| * | Merge pull request #707 from gatecat/cyclonev | gatecat | 2021-05-15 | 31 | -9/+4222 | |
| |\ | | | | | mistral: Initial Cyclone V support | |||||
| | * | Update README | gatecat | 2021-05-15 | 1 | -0/+1 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add MISTRAL_CLKBUF cell type | gatecat | 2021-05-15 | 5 | -1/+15 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | ci: Use GH only for Mistral and fpga-interchange | gatecat | 2021-05-15 | 3 | -2/+58 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Tidying up | gatecat | 2021-05-15 | 12 | -12/+13 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Make router2 the default | gatecat | 2021-05-15 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | router2: Hacky workaround for slow Cyclone V convergence | gatecat | 2021-05-15 | 1 | -3/+3 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Speed up bel binding and checking | gatecat | 2021-05-15 | 1 | -4/+18 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Workaround for weird SCLR issue | gatecat | 2021-05-15 | 1 | -0/+7 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Fix ENA and ACLR bitstream generation | gatecat | 2021-05-15 | 4 | -4/+11 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Disable global buffers that are currently broken | gatecat | 2021-05-15 | 1 | -0/+2 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | router2: Reduce verbosity when debugging | gatecat | 2021-05-15 | 1 | -0/+2 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Compensate for EF_SEL mirroring in validity check | gatecat | 2021-05-15 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Fix EF_SEL and BTO_DIS | gatecat | 2021-05-15 | 2 | -4/+5 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: PKREG bits appear to be mirrored within a half? | gatecat | 2021-05-15 | 1 | -2/+3 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Debugging flipflops | gatecat | 2021-05-15 | 1 | -3/+4 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Trim SDATA if SLOAD is low | gatecat | 2021-05-15 | 1 | -0/+9 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: FF&CLKBUF fixes, part 1 | gatecat | 2021-05-15 | 2 | -1/+10 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: First pass at FF and CLKBUF bitgen | gatecat | 2021-05-15 | 2 | -18/+115 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Account for TD input count limit | gatecat | 2021-05-15 | 4 | -9/+128 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | msitral: Fix pip iterator Python bindings | gatecat | 2021-05-15 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Implement PIP locations, too | gatecat | 2021-05-15 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Implement bounding boxes for router2 | gatecat | 2021-05-15 | 2 | -1/+15 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Debugging carry chain issues | gatecat | 2021-05-15 | 2 | -13/+34 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Adding FF control set reservation | gatecat | 2021-05-15 | 3 | -58/+148 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Carry fixes | gatecat | 2021-05-15 | 2 | -3/+16 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Carry debugging | gatecat | 2021-05-15 | 3 | -41/+11 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Write arith mode to bitstream (not yet functional) | gatecat | 2021-05-15 | 2 | -2/+18 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: First pass at carry packing | gatecat | 2021-05-15 | 4 | -8/+82 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: FF validity checking fixes | gatecat | 2021-05-15 | 1 | -7/+13 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Fix constant trimming | gatecat | 2021-05-15 | 2 | -1/+2 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Write LUT inits | gatecat | 2021-05-15 | 2 | -1/+72 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add some IO configuration | gatecat | 2021-05-15 | 1 | -0/+30 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Setting some more boilerplate bits | gatecat | 2021-05-15 | 3 | -1/+118 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add stub RBF generation | gatecat | 2021-05-15 | 4 | -9/+108 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Rename clock buffer primitive | gatecat | 2021-05-15 | 2 | -2/+3 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Python and GUI stub | gatecat | 2021-05-15 | 6 | -0/+350 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Implement some misc. things | gatecat | 2021-05-15 | 4 | -10/+78 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Some preps for generating bitstreams | gatecat | 2021-05-15 | 4 | -28/+131 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Adding a function for computing ALM LUT masks | gatecat | 2021-05-15 | 2 | -0/+90 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add IO packing | gatecat | 2021-05-15 | 5 | -8/+135 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add a basic QSF parser | gatecat | 2021-05-15 | 4 | -1/+295 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add some packing logic based on nexus | gatecat | 2021-05-15 | 4 | -3/+202 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Working on FF validity checking | gatecat | 2021-05-15 | 2 | -1/+117 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| | * | mistral: Add the 'pin style' stuff based on Nexus | gatecat | 2021-05-15 | 2 | -0/+112 | |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
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index : iCE40/nextpnr | |
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