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Author
Age
Files
Lines
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Fix python version in CI
Miodrag Milanovic
2022-10-24
1
-1
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+2
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Update CI script
Miodrag Milanovic
2022-10-24
1
-6
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+6
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run clangformat
gatecat
2022-10-17
2
-7
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+12
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Merge pull request #1034 from lushaylabs/support-windows-crlf
myrtle
2022-10-17
1
-4
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+4
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support windows line endings
Lushay Labs
2022-10-09
1
-4
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+4
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Merge pull request #1035 from tyler274/patch-1
myrtle
2022-10-17
1
-1
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+1
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Correct Not Equal operator implementation in ice40
Tyler
2022-10-17
1
-1
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+1
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Merge pull request #1032 from davidlattimore/registered-output-xform
myrtle
2022-10-05
2
-0
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+9
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nexus: Transform registered output parameters
David Lattimore
2022-10-05
2
-0
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+9
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Merge pull request #1031 from YosysHQ/gatecat/fab-next
myrtle
2022-09-30
5
-2
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+130
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fabulous: Pack, validity check and FASM support for muxes
gatecat
2022-09-30
4
-5
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+84
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fabulous: Add split MUX bels
gatecat
2022-09-30
2
-1
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+50
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Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fix
myrtle
2022-09-26
1
-15
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+21
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ice40: Fix handling of carry out route-thru via 25,14
gatecat
2022-09-26
1
-15
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+21
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Merge pull request #1029 from airskywater/airskywater-patch-1
myrtle
2022-09-24
1
-0
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+6
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Modify code to meet the code style preferences
airskywater
2022-09-24
1
-4
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+4
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Add more sanity check for pointers
airskywater
2022-09-24
1
-0
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+1
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fix runtime segmentation fault
airskywater
2022-09-24
1
-0
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+5
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Merge pull request #1019 from antmicro/support-clock-relations
myrtle
2022-09-20
4
-11
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+300
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Added the --ignore-rel-clk option to control timing checks for cross-domain p...
Maciej Kurc
2022-09-20
3
-115
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+108
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Code cleanup
Maciej Kurc
2022-08-31
2
-68
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+39
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Added timing check for cross-domain paths for related clocks
Maciej Kurc
2022-08-31
1
-4
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+104
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Augmented TimingAnalyser class with detection of clock to clock relations
Maciej Kurc
2022-08-30
2
-7
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+225
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Fixed port timing classes of DCC ports in the Nexus architecture
Maciej Kurc
2022-08-30
1
-4
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+11
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Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src
myrtle
2022-09-20
2
-0
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+17
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ice40: implement checkPipAvailForNet
gatecat
2022-09-20
1
-0
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+10
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router2: Reserve source wire, too
gatecat
2022-09-20
1
-0
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+7
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fabulous: fix, but disable, IO configuration
gatecat
2022-09-16
1
-0
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+3
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Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactor
myrtle
2022-09-16
1
-1347
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+1402
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ecp5: Split bitstream generation into more functions
gatecat
2022-09-15
1
-1347
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+1402
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Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol
myrtle
2022-09-16
1
-3
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+7
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ice40: Fix UltraPlus BRAM clock polarity
gatecat
2022-09-14
1
-3
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+7
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Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixes
myrtle
2022-09-15
3
-1
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+42
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nexus: Add ES2 device names and --list-devices
gatecat
2022-09-15
3
-1
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+42
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Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaduct
myrtle
2022-09-15
12
-1
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+1637
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fabulous: Add a viaduct uarch
gatecat
2022-09-09
12
-1
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+1637
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Merge pull request #1024 from YosysHQ/gatecat/pybind11-bump
myrtle
2022-09-15
214
-10025
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+21644
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3rdparty: Bump vendored pybind11 version for py3.11 support
gatecat
2022-09-14
214
-10025
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+21644
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Merge pull request #1018 from yrabbit/bf-0
myrtle
2022-08-25
1
-0
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+2
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gowin: BUGFIX. Really memorize the chip
YRabbit
2022-08-25
1
-0
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+2
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Merge pull request #1017 from YosysHQ/routerfix
myrtle
2022-08-22
2
-5
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+4
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add missing overrides
Miodrag Milanovic
2022-08-22
1
-3
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+3
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Fix parameter order
Miodrag Milanovic
2022-08-22
1
-2
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+1
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Merge pull request #1016 from atsampson/python3
myrtle
2022-08-21
7
-16
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+16
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Use CMake's Python3 rather than PythonInterp in subdirs
Adam Sampson
2022-08-21
7
-16
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+16
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pybindings: Mark CellInfo::bel as readonly
gatecat
2022-08-18
1
-2
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+1
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Merge pull request #1014 from LAK132/master
myrtle
2022-08-18
1
-4
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+4
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Replace deprecated method of finding Python 3
LAK132
2022-08-17
1
-4
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+4
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Merge pull request #1013 from YosysHQ/gatecat/viaduct-args
myrtle
2022-08-15
1
-0
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+14
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viaduct: Allow passing command line options to uarch with -o
gatecat
2022-08-15
1
-0
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+14
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