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| * | ecp5: Improve global routing robustnessDavid Shah2020-05-141-0/+11
| * | ecp5: Don't promote VCC/GND to globals even if connected to clock portDavid Shah2020-05-141-0/+2
| * | lpf: Support // commentsDavid Shah2020-05-141-0/+3
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* | clangformatDavid Shah2020-05-162-4/+4
* | Merge pull request #442 from nategraff-sifive/fix-unsupported-spellingDavid Shah2020-05-143-10/+10
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| * | Fix spelling of 'unsupported'Nathaniel Graff2020-05-133-10/+10
* | | Merge pull request #441 from YosysHQ/eddie/fix_topoMiodrag Milanović2020-05-141-16/+16
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| * | | Fix embarassing use of topographical when meaning topologicalEddie Hung2020-05-141-16/+16
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* | | Merge pull request #439 from edbordin/masterMiodrag Milanović2020-05-141-4/+6
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| * | minor patch for MinGW buildEd Bordin2020-05-141-4/+6
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* | Merge pull request #437 from miek/lvcmos33d-driveDavid Shah2020-05-121-0/+19
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| * | ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
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* / Add missing --top optionDavid Shah2020-05-091-0/+5
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* Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings'David Shah2020-05-013-6/+125
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| * ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| * No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
| * Further condenseRoss Schlaikjer2020-04-291-11/+10
| * Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
| * Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
| * Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
| * Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
| * Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
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* Merge pull request #433 from YosysHQ/dave/pyfixesDavid Shah2020-04-242-4/+17
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| * python: Also convert regular map keys to stringDavid Shah2020-04-241-1/+3
| * python: Improve general robustness during autocompleteDavid Shah2020-04-241-0/+4
| * python: Escape strings for autocompleteDavid Shah2020-04-241-2/+8
| * python: Wrap map IdString key when accessed by indexDavid Shah2020-04-241-1/+2
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* Merge pull request #432 from smunaut/fix_disconnectDavid Shah2020-04-241-0/+1
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| * design_utils: Set port.net to null when disconnectingSylvain Munaut2020-04-241-0/+1
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* Merge pull request #428 from mmicko/masterMiodrag Milanović2020-04-201-2/+2
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| * old boost supportMiodrag Milanovic2020-04-201-2/+2
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* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
* Merge pull request #426 from YosysHQ/dave/fix-pll2eclkDavid Shah2020-04-151-1/+80
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| * ecp5: Use dedicated routing for ECLKs where possibleDavid Shah2020-04-141-1/+80
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* Add TRELLIS_PROGRAM_PREFIXMiodrag Milanovic2020-04-111-4/+6
* Merge pull request #424 from mmicko/program_prefixDavid Shah2020-04-101-10/+12
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| * Support custom PROGRAM_PREFIXMiodrag Milanovic2020-04-101-10/+12
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* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-073-4/+33
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| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-073-19/+23
| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-073-8/+16
| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
* | Merge pull request #419 from garytwong/handle-opendrainDavid Shah2020-04-071-0/+3
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| * | Handle OPENDRAIN attribute.Gary Wong2020-04-031-0/+3
* | | Merge pull request #421 from garytwong/fix-lpf-locate-assertion-failureDavid Shah2020-04-071-0/+2
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| * | | Fix assertion failure on invalid LOCATE input.Gary Wong2020-04-051-0/+2
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