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* mistral: move M10K code to packLofty2022-03-092-71/+77
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* mistral: M10K cell functionLofty2022-03-092-2/+75
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* mistral: add M10K belLofty2022-03-094-1/+78
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* clangformatgatecat2022-03-094-10/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #937 from antmicro/mdudek/nexus_implicit_DCC_cascadinggatecat2022-03-091-1/+1
|\ | | | | nexus: DCCs cannot be cascaded
| * nexus: DCCs cannot be cascadedMaciej Dudek2022-03-091-1/+1
| | | | | | | | | | | | This commit solves implicit cascading when clock signal drives DCC and logic Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #936 from whitequark/wasm-no-parallel-refinegatecat2022-03-081-1/+4
|\ \ | |/ |/| Add missing part of PR #933
| * Add missing part of commit aee35768.Catherine2022-03-081-1/+4
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* | Merge pull request #933 from whitequark/wasm-no-parallel-refinegatecat2022-03-052-1/+19
|\| | | | | Disable parallel refinement on WebAssembly
| * Disable parallel refinement on WebAssembly.Catherine2022-03-052-1/+19
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* Merge pull request #932 from ↵gatecat2022-03-044-12/+21
|\ | | | | | | | | antmicro/remove-hardcoded-values-from-lut-mapping-cache interchange: lut map cache: remove hardcoded values
| * interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-044-12/+21
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #931 from yrabbit/bugfix-0gatecat2022-03-041-0/+10
|\ \ | |/ |/| gowin: BUGFIX gui crash
| * gowin: BUGFIX gui crashYRabbit2022-03-041-0/+10
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #929 from gatecat/gatecat/parallel_refinegatecat2022-03-035-2/+1012
|\ \ | | | | | | parallel_refine: New, parallelised placement refinement pass
| * | parallel_refine: New, parallelised placement refinement passgatecat2022-03-035-2/+1012
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* | Merge pull request #925 from YosysHQ/gatecat/netlist-ivgatecat2022-03-0134-457/+701
|\ \ | | | | | | Switch to potentially-sparse net users array
| * | Switch to potentially-sparse net users arraygatecat2022-02-2734-465/+442
| | | | | | | | | | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
| * | Add indexed_store container typegatecat2022-02-262-0/+267
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #927 from YosysHQ/gatecat/ecp5-pdpw-fixgatecat2022-02-281-1/+1
|\ \ \ | |/ / |/| | ecp5: Fix PDPW16K clock param renaming
| * | ecp5: Fix PDPW16K clock param renaminggatecat2022-02-281-1/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #924 from Ravenslofty/okamigatecat2022-02-257-1/+638
|\ \ | | | | | | okami: new Viaduct arch
| * | okami: new Viaduct archLofty2022-02-247-1/+638
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* | Merge pull request #923 from yrabbit/partnumber-regatecat2022-02-241-1/+1
|\ \ | |/ |/| gowin: recognize partnumbers of GW1NZ-1
| * gowin: recognize partnumbers of GW1NZ-1YRabbit2022-02-241-1/+1
|/ | | | | | | | | | | The model should be recognized by the partnumber, --family is needed only if the same partnumbers belong to different models. This is done in order to automatically generate parameters for calling nextpnr from Gowin files without problems: there also only partnumber is used and only in some cases the model is specified with the -name parameter and GW1NZ-1 is not such a case. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #922 from yrabbit/wip-0-lvdsgatecat2022-02-232-0/+87
|\ | | | | gowin: Add support for true differential output
| * gowin: Add support for true differential outputYRabbit2022-02-232-0/+87
|/ | | | | | | | | The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #921 from YosysHQ/gatecat/concat-overridesgatecat2022-02-201-0/+4
|\ | | | | Add IdStringList::concat overrides taking IdString
| * Add IdStringList::concat overrides taking IdStringgatecat2022-02-201-0/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #913 from chiplet/gw1nz-1gatecat2022-02-202-2/+2
|\ \ | |/ |/| gowin: Add GW1NZ-1 support
| * gowin: bump apycula versionVerneri Hirvonen2022-02-161-1/+1
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| * gowin: Add GW1NZ-1Verneri Hirvonen2022-02-151-1/+1
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* | Merge pull request #919 from YosysHQ/gatecat/netlist-iiigatecat2022-02-1834-768/+765
|\ \ | | | | | | refactor: New member functions to replace design_utils
| * | refactor: New member functions to replace design_utilsgatecat2022-02-1834-768/+765
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #918 from YosysHQ/gatecat/netlist-iigatecat2022-02-1643-2280/+2790
|\ \ | | | | | | Refactor pt2, barnacle cleanup
| * | refactor: Use constids instead of id("..")gatecat2022-02-1641-2137/+2686
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | refactor: Use cell member functions to add portsgatecat2022-02-165-361/+322
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #917 from YosysHQ/gatecat/netlist-igatecat2022-02-1618-170/+95
|\ \ | | | | | | refactor: New NetInfo and CellInfo constructors
| * | refactor: New NetInfo and CellInfo constructorsgatecat2022-02-1618-170/+95
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* | mistral: Fix 'not handled in switch' compiler warninggatecat2022-02-161-1/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2022-02-161-7/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #914 from ept221/doc_updategatecat2022-02-161-1/+1
|\ \ | |/ |/| Fixed formatting typo in archapi.md
| * Fixed formatting typo in archapi.mdEzra Thomas2022-02-151-1/+1
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* Merge pull request #912 from danc86/nexus-osca-7percentgatecat2022-02-101-1/+1
|\ | | | | nexus: reduce OSCA worst case to 7%
| * nexus: reduce OSCA worst case to 7%Dan Callaghan2022-02-101-1/+1
|/ | | | | | | | | | | The current version of Crosslink-NX Family Data Sheet lists the high frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher than its nominal 450MHz): https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780 Older documents listed a wider frequency range but ±7% is the range for production parts.
* Merge pull request #908 from YosysHQ/gatecat/generic-fanout-blockgatecat2022-02-062-2/+5
|\ | | | | viaduct: Allow constraining only cascades without fanout
| * viaduct: Allow constraining only cascades without fanoutgatecat2022-02-042-2/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #909 from pepijndevos/mygw1n9cgatecat2022-02-063-8/+13
|\ \ | | | | | | Add support for GW1N-9C and --family argument
| * | add GW1N-9C dbPepijn de Vos2022-02-062-2/+2
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| * | gowin: add an option to manually specify familyIcenowy Zheng2022-02-061-6/+11
|/ / | | | | | | | | | | | | | | | | | | | | In the vendor IDE, there's a device family named GW1N-9C (which seems to mean C revision of GW1N-9), in which the model numbers are all the same with GW1N-9. Add an option to nextpnr-gowin to allow manually specified family for this situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 17:51:16 +0000