| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | interchange: Allow pseudo pip wires to overlap with bound site wires on the ↵ | gatecat | 2021-07-06 | 3 | -17/+13 |
| | | | | | | | same net Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | router2: Dump pre-bound routes when routing fails in debug mode | gatecat | 2021-07-06 | 1 | -1/+11 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Improve search for PAD-attached bels | gatecat | 2021-07-06 | 2 | -41/+32 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: tests: add obuftds test | Alessandro Comodi | 2021-07-06 | 6 | -0/+80 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #748 from acomodi/fix-phys-net-writing | gatecat | 2021-07-02 | 1 | -2/+13 |
| |\ | | | | | interchange: phys: skip only nets writing on disconnected out ports | ||||
| | * | interchange: phys: skip only nets writing on disconnected out ports | Alessandro Comodi | 2021-07-02 | 1 | -2/+13 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #747 from cr1901/machxo2 | gatecat | 2021-07-01 | 9 | -13/+140 |
| |\ | | | | | MachXO2 Checkpoint 1 | ||||
| | * | machxo2: Fix packing for directly-connected DFFs. | William D. Jones | 2021-07-01 | 3 | -9/+28 |
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| | * | machxo2: Add VHDL primitives, demo, and script. | William D. Jones | 2021-07-01 | 4 | -0/+81 |
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| | * | machxo2: Add a special case for pips whose config bits are in multiple | William D. Jones | 2021-07-01 | 1 | -0/+12 |
| | | | | | | | | | tiles. | ||||
| | * | machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output. | William D. Jones | 2021-07-01 | 1 | -2/+17 |
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| | * | machxo2: Set Pip and Wire delays to reasonable fake values mirroring | William D. Jones | 2021-07-01 | 1 | -2/+2 |
| | | | | | | | | | estimateDelay. | ||||
| * | | Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const | gatecat | 2021-07-01 | 1 | -5/+9 |
| |\ \ | | | | | | | interchange: Handle canInvert PIPs when processing preferred constants | ||||
| | * | | interchange: Handle canInvert PIPs when processing preferred constants | gatecat | 2021-07-01 | 1 | -5/+9 |
| | |/ | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #745 from YosysHQ/gatecat/ic-node-source | gatecat | 2021-07-01 | 1 | -0/+5 |
| |\ \ | |/ |/| | interchange: Handle case where routing source is a node | ||||
| | * | interchange: Handle case where routing source is a node | gatecat | 2021-07-01 | 1 | -0/+5 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | clangformat | gatecat | 2021-07-01 | 1 | -1/+5 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #744 from YosysHQ/gatecat/const-in-macro | gatecat | 2021-07-01 | 1 | -1/+1 |
| |\ | | | | | interchange: Fix handling of constants in macros | ||||
| | * | interchange: Fix handling of constants in macros | gatecat | 2021-07-01 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports | gatecat | 2021-07-01 | 5 | -0/+69 |
| |\ \ | | | | | | | interchange: Reserve site ports only reachable from dedicated routing | ||||
| | * | | interchange: Reserve site ports only reachable from dedicated routing | gatecat | 2021-07-01 | 5 | -0/+69 |
| | |/ | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-nets | gatecat | 2021-07-01 | 1 | -1/+12 |
| |\ \ | |/ |/| | interchange: phys: do not output nets which have no users | ||||
| | * | interchange: phys: do not output nets which have no users | Alessandro Comodi | 2021-07-01 | 1 | -1/+12 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #741 from acomodi/fix-ded-interc | gatecat | 2021-06-30 | 1 | -8/+14 |
| |\ | | | | | interchange: fix dedicated interconnect exploration | ||||
| | * | interchange: fix dedicated interconnect exploration | Alessandro Comodi | 2021-06-30 | 1 | -8/+14 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #739 from YosysHQ/gatecat/usp-io-macro | gatecat | 2021-06-30 | 5 | -1/+91 |
| |\ | | | | | interchange: Place entire IO macro based on routeability | ||||
| | * | interchange: Fix dedicated interconnect check when site is the same | gatecat | 2021-06-30 | 1 | -1/+4 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Place IO macro content based on routing | gatecat | 2021-06-30 | 1 | -0/+79 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Track the macros that cells have been expanded from | gatecat | 2021-06-29 | 3 | -0/+8 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #738 from YosysHQ/json_load_reinit | gatecat | 2021-06-30 | 3 | -11/+11 |
| |\ \ | | | | | | | Preserve ArchArgs and reinit Context when applicable in GUI, fixes #737 | ||||
| | * | | Preserve ArchArgs and reinit Context when applicable in GUI | Miodrag Milanovic | 2021-06-30 | 3 | -11/+11 |
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| * / | loading json should be disabled in this place | Miodrag Milanovic | 2021-06-30 | 1 | -1/+1 |
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| * | Merge pull request #736 from YosysHQ/gatecat/pp-multi-output | gatecat | 2021-06-28 | 1 | -13/+2 |
| |\ | | | | | interchange: Allow site wires driven by more than one bel | ||||
| | * | interchange: Allow site wires driven by more than one bel | gatecat | 2021-06-28 | 1 | -13/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpin | gatecat | 2021-06-28 | 1 | -1/+1 |
| |\ \ | |/ |/| | interchange: Handle disconnected bel pins in dedicated interconnect | ||||
| | * | interchange: Handle disconnected bel pins in dedicated interconnect | gatecat | 2021-06-28 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #734 from acomodi/remove-rw-patch | gatecat | 2021-06-24 | 1 | -3/+0 |
| |\ | | | | | ci: remove RapidWright patching | ||||
| | * | ci: remove RapidWright patching | Alessandro Comodi | 2021-06-24 | 1 | -3/+0 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #733 from acomodi/interchange-move-macro-before-io | gatecat | 2021-06-18 | 1 | -1/+1 |
| |\ | | | | | interchange: arch: move macro expansion step before ios packing | ||||
| | * | interchange: arch: move macro expansion step before ios packing | Alessandro Comodi | 2021-06-18 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #731 from YosysHQ/gatecat/timing-mem-error | gatecat | 2021-06-17 | 1 | -4/+11 |
| |\ | | | | | sta: Fix a memory error introduced by using dict instead of unordered_map | ||||
| | * | sta: Fix a memory error introduced by the dict move | gatecat | 2021-06-17 | 1 | -4/+11 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #730 from YosysHQ/gatecat/dcc-routehtru | gatecat | 2021-06-17 | 3 | -3/+62 |
| |\ | | | | | nexus: Fix some 17k reliability issues | ||||
| | * | nexus: Disable center DCC-thrus on 17k device | gatecat | 2021-06-16 | 3 | -1/+29 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | nexus: Fix FASM gen for DCC-thru | gatecat | 2021-06-16 | 1 | -3/+34 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #728 from YosysHQ/gatecat/nexus-ram | gatecat | 2021-06-15 | 7 | -2/+384 |
| |\ | | | | | interchange/nexus: Add RAM techmap rule and a RAM test | ||||
| | * | interchange: Bump versions | gatecat | 2021-06-15 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | nexus: Add modified version of RAM test | gatecat | 2021-06-15 | 5 | -0/+206 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules | gatecat | 2021-06-15 | 1 | -0/+176 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #729 from acomodi/interchange-fix-phys-net-writer | gatecat | 2021-06-15 | 1 | -5/+2 |
| |\ \ | | | | | | | interchange: fix phys net writer | ||||
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index : iCE40/nextpnr | |
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