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* Merge pull request #993 from yrabbit/lw-wip-1myrtle2022-06-075-8/+299
|\ | | | | gowin: Add support for long wires
| * gowin: Add support for long wiresYRabbit2022-05-275-8/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #992 from antmicro/mdudek/nexus_write_dccmyrtle2022-05-271-3/+2
|\ \ | | | | | | Change write_dcc to work with tilegroups from prjoxide
| * | Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
| |/ | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #990 from YosysHQ/gatecat/fix-988myrtle2022-05-221-5/+0
|\ \ | | | | | | Don't assert on mixed domain paths in report
| * | Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #989 from YosysHQ/lofty/cmake-bumpmyrtle2022-05-211-1/+1
|\ \ | |/ |/| Bump minimum CMake to 3.13
| * Bump minimum CMake to 3.13Lofty2022-05-211-1/+1
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* Merge pull request #985 from antmicro/interchange-lut-constantsmyrtle2022-05-135-58/+180
|\ | | | | [interchange] Tying unused LUT inputs according to architecture
| * Added fallback to VCC as the preferred constant if the architecture does not ↵Maciej Kurc2022-05-123-6/+20
| | | | | | | | | | | | specify one. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added tying unused LUT pins to preferred constant instead of VccMaciej Kurc2022-05-111-2/+8
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-115-58/+160
|/ | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #984 from yrabbit/assertmyrtle2022-05-101-1/+1
|\ | | | | common: Correct a minor typo in the message
| * common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fixmyrtle2022-05-081-7/+24
|\ | | | | ice40: Fix propagation of constraints through SB_GB
| * ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #981 from yrabbit/lw-cst-0gatecat2022-05-031-7/+27
|\ | | | | gowin: Add initial syntax support for long wires
| * gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
| | | | | | | | | | | | | | Only the recognition of the directive in the .CST file and elementary checks are added, but not the long-wire mechanism itself. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | generic: Add some extra helpers for viaduct uarchesgatecat2022-05-024-4/+52
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add missing uarch guardgatecat2022-04-271-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #977 from YosysHQ/gatecat/prefine-tileswapgatecat2022-04-192-1/+100
|\ | | | | prefine: Do full-tile swaps, too
| * prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #976 from YosysHQ/gatecat/dp-reworkgatecat2022-04-175-545/+730
|\ | | | | Move general parallel detail place code out of parallel_refine
| * Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fixgatecat2022-04-121-34/+45
|\ | | | | ice40: Avoid chain finder from mixing up chains by only allowing I3 c…
| * ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ↵gatecat2022-04-111-34/+45
|/ | | | | | at end Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #974 from YosysHQ/gatecat/ci-restructuregatecat2022-04-0816-125/+301
|\ | | | | ci: Restructure and move entirely to GH actions from Cirrus
| * ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-0816-125/+301
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #973 from YosysHQ/gatecat/folder-tidygatecat2022-04-0875-3/+6
|\| | | | | Split up common into kernel,place,route
| * Split up common into kernel,place,routegatecat2022-04-0875-3/+6
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2gatecat2022-04-0713-1349/+1137
|\ | | | | ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
| * ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0713-1349/+1137
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* | Merge pull request #971 from modwizcode/fix-tbb-macosgatecat2022-04-061-1/+1
|\ \ | |/ |/| cmake: properly include TBB libraries.
| * cmake: properly include TBB libraries.Irides2022-04-051-1/+1
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* generic: Allow bel pins without wiresgatecat2022-04-041-3/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #970 from yrabbit/nr9-wipgatecat2022-04-034-2/+40
|\ | | | | gowin: handle the GW1N-9 feature.
| * gowin: handle the GW1N-9 feature.YRabbit2022-04-034-2/+40
|/ | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2022-03-313-12/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fixgatecat2022-03-311-1/+1
|\ | | | | ice40: Fix wirenames containing / which is the list separator
| * ice40: Fix wirenames containing / which is the list separatorgatecat2022-03-301-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #968 from tpambor/gowin-osc-fixgatecat2022-03-302-5/+6
|\ \ | |/ |/| gowin: Fix z-index of oscillator
| * gowin: Fix z-index of oscillatorTim Pambor2022-03-302-5/+6
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* Merge pull request #952 from antmicro/mdudek/nexus_pllgatecat2022-03-303-27/+177
|\ | | | | Nexus: Fixed OSCA parameters, add pll default parameters
| * Rename parse_lattice_param to parse_lattice_param_from_cellMaciej Dudek2022-03-303-36/+46
| | | | | | | | | | | | | | | | | | Add new definition for parse_lattice_param Now parse_lattice_param is design to parse Property rather than search for it in cell. This functionalty was move to parse_lattice_param_from_cell. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Nexus: Fixed OSCA parameters, add pll default parametersMaciej Dudek2022-03-181-2/+142
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #966 from YosysHQ/gatecat/ice40-optgatecat2022-03-294-4/+91
|\ \ | | | | | | ice40: Merge driving LUT<=2s into carry-only LCs
| * | ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-294-4/+91
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #960 from YosysHQ/gatecat/viaduct-docsgatecat2022-03-292-2/+137
|\ \ \ | | | | | | | | First pass viaduct docs
| * | | docs: Initial reference for the Viaduct 'uarch' APIgatecat2022-03-212-2/+137
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-18 03:40:12 +0000