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* Fix Cygwin buildgatecat2021-10-011-1/+1
* Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fixgatecat2021-09-303-7/+10
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| * interchange: Fix compile warningsgatecat2021-09-282-6/+9
| * ci: Enable -Werror for interchange archgatecat2021-09-281-1/+1
* | Merge pull request #810 from antmicro/write-timing-reportgatecat2021-09-297-158/+539
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| * | Code formattingMaciej Kurc2021-09-294-119/+87
| * | Brought back printout of critical path source file references, added clk-to-q...Maciej Kurc2021-09-293-28/+74
| * | Shifted moving of data containers after printingMaciej Kurc2021-09-281-11/+11
| * | Added a commandline option controlled writeout of per-net timing detailsMaciej Kurc2021-09-284-9/+22
| * | Added description of the JSON report structure.Maciej Kurc2021-09-281-1/+73
| * | Moved timing result report storage to the context, added its writeout to the ...Maciej Kurc2021-09-286-282/+279
| * | Added reporting critical paths in JSON formatMaciej Kurc2021-09-281-25/+49
| * | Decoupled critical path report generation from its printingMaciej Kurc2021-09-281-134/+264
| * | Switched to JSON format for timing analysis reportMaciej Kurc2021-09-281-33/+81
| * | Added writing a CSV report with timing analysis of each net branchMaciej Kurc2021-09-284-6/+89
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* | Merge pull request #830 from yrabbit/mistypegatecat2021-09-291-1/+1
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| * Fix mistype.YRabbit2021-09-291-1/+1
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* Merge pull request #827 from YosysHQ/gatecat/idstring-ingatecat2021-09-271-0/+10
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| * idstring: Add 'in' functiongatecat2021-09-271-0/+10
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* Merge pull request #812 from antmicro/MacroCellsgatecat2021-09-277-22/+572
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| * Fix small isses and code formattingMaciej Dudek2021-09-275-148/+150
| * Break up macro_cluster_placement into smaller functionsMaciej Dudek2021-09-241-20/+33
| * Update python-fpga-interchange to v0.0.20Maciej Dudek2021-09-231-1/+1
| * Fix AC-3 algorithmMaciej Dudek2021-09-231-9/+17
| * Improve macro cluster placementMaciej Dudek2021-09-231-235/+41
| * Change Cluster placement algorithmMaciej Dudek2021-09-233-123/+133
| * Adding MacroCell placementMaciej Dudek2021-09-234-21/+353
| * Adding support for MacroCellsMaciej Dudek2021-09-235-6/+385
* | ci: Bump prjoxide versiongatecat2021-09-241-1/+1
* | Merge pull request #826 from YosysHQ/gatecat/nexus-lutpermgatecat2021-09-246-6/+100
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| * nexus: Add resource cost overridesgatecat2021-09-242-2/+21
| * router2: Allow overriding resource costsgatecat2021-09-242-2/+9
| * nexus: LUT permutation supportgatecat2021-09-244-4/+72
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* Merge pull request #825 from antmicro/chain_swap_fixgatecat2021-09-231-2/+15
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| * Fix chain swapMaciej Dudek2021-09-231-2/+15
* | Merge pull request #822 from YosysHQ/gatecat/nexus-split-vccgatecat2021-09-233-0/+7
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| * | nexus: Support for split Vcc routinggatecat2021-09-223-0/+7
* | | Merge pull request #824 from YosysHQ/gatecat/py-sigintgatecat2021-09-231-1/+7
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| * | python: Restore SIGINT handler while running a Python scriptgatecat2021-09-221-1/+7
* | | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaksgatecat2021-09-222-2/+4
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| * | nexus: Tweaks for router1 performancegatecat2021-09-222-2/+4
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* | Merge pull request #821 from YosysHQ/gatecat/dsp-fixgatecat2021-09-225-36/+80
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| * placer1: Remove redundant relative constraint checkgatecat2021-09-221-4/+0
| * nexus: Fix DSP macro placementgatecat2021-09-224-32/+80
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* Merge pull request #815 from antmicro/nexus-fix-siologic-handlinggatecat2021-09-202-2/+234
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| * Added support for syn_useioff for enabling tri-state control FF integration i...Maciej Kurc2021-09-201-13/+23
| * Use correct names for IDDRX1_ODDRX1 FASM featuresMaciej Kurc2021-09-172-22/+4
| * Added automatic inference and integration of FFs driving T pin into IOLOGICMaciej Kurc2021-09-172-16/+177
| * Added handling of the case when tri-state control net bypasses SIOLOGIC belMaciej Kurc2021-09-171-2/+81
* | placer1: Fix cluster swap cost updatesgatecat2021-09-181-8/+4
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